FPGA Application Briefs

• 3200DX Dual-Port Random Access Memory (RAM)
• 3200DX Wide Decode Modules
• IEEE Standard 1149.1 (JTAG) in the 3200DX Family
• 3200DX Quadrant Clocks
• Fast On and Off Chip Delays with 1200XL and 3200DX I/O Latches
• Using ACT 3 Family I/O Macros
• Implementing Three-State and Bidirectional Buses with Multiplexers in Actel FPGAs
• Global Clock Networks
• Designing State Machines for FPGAs
• Implementing Multipliers with Actel FPGAs
  
  Design Files dt1.exe

  Synchronous Dividers in Actel FPGAs
  

  Design Files dt4.exe

  Using FPGAs for Digital PLL Applications

  Oscillators for Actel FPGAs

  Field Upgradability Using Actel One-Time-Programmable FPGAs

  Using the Silicon Explorer for System-level Debug

  A Power-on Reset (POR) Circuit for Actel Devices

  Three-Stating Actel Device I/O Pins for Board Level Testing

  Using Actel Devices in Hot-Socketing Applications