목차
PPT 슬라이드
PPT 슬라이드
Agenda
Altera Business and Technology Overview
The Programmable Solutions CompanyTM
Highlights
Worldwide Research & Development
Worldwide Manufacturing Capacity
Revenue by Market Segment
Altera Communications Solutions
Component Overview
APEX: Multi-Million-Gate Device
ACEX: High Performance at Low Cost
Price Trend
Intellectual Property
Quartus™ Development Software
System-on-a-Programmable-Chip Solution
Process Geometry Migration
Gate Delays
Aluminum-Copper Interconnect
Programmable Logic Capacity
ASIC vs. PLD Density
Minimum Order Quantities
CMOS Digital Logic Market
The Future of System Design
Altera PLD vs. DSP
Implementing FIR Filter with Altera
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Summary
W-CDMA System Implementation with Altera
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Wireless/Wireless Data Growth
Mobile Multimedia: IMT-2000
International Mobile Telephony for the year 2000 (IMT-2000)
Programmable Solution - The Right Solution for 3G
3G W-CDMA Overview
3G W-CDMA Overview (cont.)
Air Interface Details
W-CDMA Signal Generation (Uplink/Downlink)
W-CDMA Transmitter Architecture
W-CDMA Receiver Architecture
Altera Solution for Key 3G Blocks
Cyclic Redundancy Check
3G Specs: Convolutional Encoder
Convolutional Encoder Solution
Convolutional Encoder Schematic
3G Specs: Viterbi Decoder
Viterbi Decoder Solution
3G Specs: Turbo Encoder
Turbo Encoder Solution
3G Specs: Turbo Decoder
Turbo Decoder Solution
3G Specs: Pseudo Noise Generator
Pseudo Noise Generator Solution
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Traditional IF-Based Transmitter
Digital I/Q - Modulator
3G Specs: QPSK Modulation
QPSK Modulator Solution
QPSK Modulator Schematic
FIR Compiler - Root Raised Cosine
NCO MegaWizard
NCO MegaWizard (cont..)
Multiplier MegaWizard
Multiplier MegaWizard
RAKE Receiver
Complex Amplitude Estimation
Multi-user Detection / Interference Cancellation
Wide-band SIC
Wideband SIC (cont..)
Narrowband SIC
Binary Correlator
Sequential Correlator
Parallel Correlator
Echo Canceller
Basics of Echo Cancellation
Evolutionary GSM Core Network
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Echo Canceller MegaWizard
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Conclusion
Forward Error Correction Products
Agenda
Viterbi Decoder
Viterbi Decoder Features
Convolutional Encoder
Trellis Diagram
Viterbi Decoder Block Diagram
Soft decision information
Code Rates and Puncturing
Convolutional Coding Summary
Viterbi Decoder MegaCore Functions
Parameters
BER Testing and Verification
Viterbi Decoder Deliverables
Performance
Turbo Encoder/Decoder
Turbo Codec in a PLD Article
Turbo Encoder/Decoder Features
Turbo Encoder/Decoder Features (cont..)
Turbo Coding System Level Description
System Level Turbo Encoding
System Level Turbo Decoding
Turbo Decoder Block Diagram
Turbo Decoder Operation
max-logMAP Decoder
3GPP Interleaver
Turbo MegaWizard
Turbo Decoder Performance
Logic and Memory Requirements
Example Turbo Decoder Configurations
Turbo Decoder Bit Error Rate
FIR Filter Compiler
Features
Features (Continued)
Complete Design Environment
Complete Design Environment
FIR Specification Flow
Step 1: Input Bus Specification
Step 2: Output Precision Specification
Step 3: Coefficient Specification
Step 4: Coefficients Scaling
Step 5: Scaling Analysis
Step 6: Architecture Setting
Step 7: Verification Output Files
MATLAB - Simulink Interface
NCO Compiler
Digital NCO Compiler
NCO Compiler Features
Features (Continued)
Dynamically Generated Matlab Interface
Dynamically Generated Verilog
NCO Compiler Function
NCO Compiler Implementation
NCO Compiler Implementation
Included Reference Designs
QPSK Modulator: Reference Design
Direct Digital Synthesizer: Ref. Design
All Digital PLL: Reference Design
Design Techniques using LPM (Library of Parameterized Modules)
LPM Features: Basic Building Blocks
LPM Support in Quartus and MAX+PLUS II
Fundamental DSP Building Blocks
LPM_ADD_SUB: Parameterized Adder/Subtractor
LPM_ADD_SUB: Pipeline Parameter
Adder1,2.gdf
Using LPM_ADD_SUB: Signed Numbers
Adder3.gdf
Adder5.gdf
LPM_MULT: Parameterized Multiplier
Using LPM_MULT
mult2.gdf
mult4.gdf
LPM_SHIFTREG: Parameterized Shift Register
Using LPM_SHIFTREG for 3G blocks
FIR Filter Implementation using LPMs
FIR Characteristics
General FIR Filter Equation
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FLEX / APEX FIR Implementation
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LUT-Based Vector Multiplier: Example
Computing First Partial Product
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4-Input, 2-Bit Parallel Vector Multiplier
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Increasing Performance
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Utilizing Symmetry in the Coefficients
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Ways To Reduce The Computation
Altera Products Update
Component Update
APEX Architecture
APEX 20KE Features
APEX 20KE Availability
ACEX: High Performance at Low Cost
ACEX 1K Availability
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MAX 7000B Overview
MAX 7000B Device Features
MAX 7000B Availability
Intellectual Property Core Products Update
Bus Interface IP Available
Communications IP Available
Signal-Processing IP Available
Processor IP Available
Peripheral IP Available
Development Tools Update
Development Tools Update
OEM Partnership
Entry-Level Tools: Free Web Download
Real-Time Hardware Verification Method
Verification Options Are Restricted
SignalTap Logic Analysis Solution
SignalTap Plus Capability
Signal Tap Plus System Analyzer
Development Boards
FLEX PCI Development Kit
SOPC Development Board
Summary
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작성한 사람: Altera Corporation
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