Implementing FIR Filter with Altera

20

40

60

80

100

Typical DSP Processor

Altera Parallel FIR Implementation

Altera Serial FIR Implementation

MIPS/$

Ten Times More

Cost Effective

This benchmark is for a symmetric FIR filter (50 taps, 8-bit data, 12-bit coefficient resolution) targeting an Altera EP20K100 APEXTM device and a TI TMS320C54x (50 MHz) DSP processor

• 10x High-performance cost advantage over standard DSP processors

• Shorten complex, high-speed FIR filter design time from six weeks to just one day

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