Complete Design Environment

• Built-in coefficient generation or import coefficients from Third-Party Tools (MATLAB®)

• Floating point to fixed point conversion plus analysis

• Models and testbeds for both Verilog HDL and VHDL

• MATLAB and Simulink® Integration

• Reference designs supplied with the compiler

• Resource estimator allows user to interactively trade-off area/speed without compiling

• FLEX® 10K and APEXTM 20K Family

* MATLAB and Simulink are registered trademarks of The MathWorks, Inc.

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