Altera's Introduction to Verilog

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Altera's Introduction to Verilog
Course Objectives
Course Outline
Verilog Overview
PPT 슬라이드
Verilog History
PPT 슬라이드
Terminology
Behavior Modeling
Structural Modeling
More Terminology
RTL Synthesis
Verilog vs. Other HDL Standards
Verilog vs. Other HDL Standards
PPT 슬라이드
PPT 슬라이드
PPT 슬라이드
Verilog - Basic Modeling Structure
Components of a Verilog Module
Components of a Verilog Module
Schematic Representation - MAC
Verilog Model: Mulitiplier-Accumulator (MAC)
PPT 슬라이드
Ports
PPT 슬라이드
Data Types
Net Data Type
PPT 슬라이드
Register Data Types
PPT 슬라이드
Memory
Parameter
Data Type
PPT 슬라이드
Assigning Values - Numbers and Operators
Assigning Values - Numbers
Numbers
Numbers
Short Quiz
Answers
Arithmetic Operators
Bitwise Operators
Reduction Operators
Relational Operators
Equality Operators
Logical Operators
Shift Operators
Miscellaneous Operators
Operator Precedence
PPT 슬라이드
Behavioral Modeling
Continuous Assignments
Continuous Assignments: Characteristics
PPT 슬라이드
Continuous Assignment - Example
PPT 슬라이드
Simulation Time
One Type of Continuous Assignment Delay
Behavioral Modeling
Two Structured Procedures (Blocks)
Two Procedural Blocks
Initial Block
Initial Block
Initial Block Example
Always Block
Always Block
Characteristics
Always Block - Example
Always/Initial Blocks
Procedural Assignments
Procedural Assignments
Two types of Procedural Assignments
Blocking vs. Nonblocking Assignments
Simulation Time
3 Delay Controls for Procedural Assignment
Regular Delay Control
Intra-assignment Delay Control
Zero Delay Control
PPT 슬라이드
Processes and Behavioral Statements
Sensitivity List
PPT 슬라이드
Combinatorial Process
Behavioral Statements
If-Else Statements
If-Else Statements
Laboratory Exercise 2
Case Statement
Case Statement
Two Other Forms of Case Statements
Laboratory Exercise 3
Loop Statements
Forever and Repeat Loops
While Loop
For Loop
Clocked Process
Functional Latch vs. Functional Flipflop
Synchronous vs. Asynchronous
Clock Enable
Functional Counter
PPT 슬라이드
PPT 슬라이드
Block Execution
Two Types of Block Executions
Sequential vs. Parallel Blocks
Behavioral Modeling
PPT 슬라이드
Verilog Functions and Tasks
PPT 슬라이드
Function Definition - Multiplier
PPT 슬라이드
PPT 슬라이드
Task Definition - Statemachine Output
Task Invocation - Statemachine
Differences
Review - Behavioral Modeling
Structural Modeling
Levels of Abstraction
Stuctural Modeling
Verilog Structural Modeling
Verilog Structural Modeling
Instantiation of Gate Primitives
Connecting ports by ordered list
User-Defined Primitives (UDP)
UDP - Latch
UDP - Register
PPT 슬라이드
Connecting ports by ordered list or by name
Port Connection Rules
Defparam
PPT 슬라이드
PPT 슬라이드
Gate Delays
Min/Typ/Max Values
Verilog Summary
Verilog Environment
Verilog - Design Block
Verilog - Stimulus Block
Verilog - System Stimulus Block
Verilog Environment
Verilog
PPT 슬라이드
PPT 슬라이드
Verilog
PPT 슬라이드
Appendix
System Tasks and Functions
Compiler Directives
Compiler Directives
Conditional Compilation
Timing Specifications
Specify Blocks
Parallel Connection
Full Connection
Specparam
Rise, Fall, Turn-off and Min/Typ/Max Values
Timing Checks
OVI Synthesis Guidelines
OVI Synthesis Guidelines
OVI Synthesis Guidelines
OVI Synthesis Guidelines

작성한 사람: Oliver Tan

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