PPT 슬라이드

Verilog Structure

• Verilog HDL : Consists of Keywords, syntax and semantics used to describe hardware functionality and timing.

• PLI : Programming Language Interface provides C language routines used to interact between Verilog and EDA tools. (Simulators,Waveform displays)

• SDF : Standard Delay Format - a file used to back-annotate accurate timing information to simulators and other tools.

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

그래픽 버전 보기