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assign adder_out = mult_out + out;
always @ (posedge clk or posedge clr)
multa u1(.in_a(ina), .in_b(inb), .m_out(mult_out));
$setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
module mult_acc (out, ina, inb, clk, clr);
wire [15:0] mult_out, adder_out;