Verilog Functions and Tasks
Function and Tasks are subprograms.
Useful for code that is repetitive in module
Add to module readability
Function
- Return a value based on its inputs
- Produces combinatorial logic
- Used in expressions: assign mult_out = mult (ina, inb);
Tasks
- Like procedures in other languages
- Can be combinatorial or registered.
- Task are invoked as statement: stm_out (nxt, first, sel, filter);