Verilog Structural Modeling

• Component Level Modeling - instantiating user-created lower-level designs (components)

• Gate Level Modeling - instantiating Verilog built-in gate primitives

  • and, nand, or, nor, xor, xnor
  • buf, bufif0, bufif1, not, notif0, notif1

• Switch Level Modeling - instantiating Verilog built-in switch primitives

  • nmos, rnmos, pmos, rpmos, cmos, rcmos
  • tran, rtran, tranif0, rtranif0, tranif1, rtrainif1, pullup, pulldown
  • Switch level modeling will not be discussed

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