목차
Designing with
MAX+PLUS II
Class Goals
Class Agenda
Introduction to Altera & Altera Devices
Introduction
to Altera
MAX+PLUS II Design Environment
MAX+plus II
MAX+PLUS
II IS...
MAX+PLUS II Can...
Or...
MAX+PLUS II Operating Environment
MAX+PLUS II Application
Suite
Questions about MAX+PLUS II?
MAX+PLUS II Design Methodology
Design
Entry
Design Entry Process
Project Setup/Management
Set Up A New Project
Design
Entry Files
Graphic Design Entry Process
Resource Libraries
Value
added Libraries
Add User Resource Libraries
Open New File & Enter
Symbols
Making Connections
Graphic Editor Options
Save & Check the Design
Message Processor
Generate
Symbols and Include Files
Symbol Editor
More on LPM Libraries
Non Megawizard LPM
Using MegaWizard Plug-In Manager
Accessing the MegaWizard
New vs
Existing Megafunction
Available Megafunctions & Output File
Customizing
the Megafunction
Files generated by the MegaWizard
Entering Customized Megafunction
Make Changes
to Customized Megafunction
Text Design Entry
AHDL
VHDL
Verilog
Waveform Design Entry
Imported Design
MAX+PLUS II Hierarchy Display
Lab1
Design Entry Recommendations
Design
Entry Summary
Compilation
MAX+PLUS II Compiler
Compiler Input and Output Files
Compiler Input Files
Compiler
Output Files
For EDIF Netlist Input
VHDL Netlist Reader Settings
For EDIF Netlist Output
Verilog
Netlist Writer & Writer Settings
VHDL Netlist Writer &
Writer Settings
Compiling a Project
The Functional Compilation Process
The Timing Compilation
Process
Compiler Processing Options
Assignments Control
Assignments
Making
Device Assignment
Making Pin Assignment
Logic Synthesis Style
Global Project Logic Synthesis Style
Assign Logic Synthesis
Style Locally
Individual Logic Option Assignment
Location assignments
Clique
Assignments
Timing Requirements Assignments
Assignment Recommendation
Ignore or Clear Assignments
Global Project Device
Options
More Compiler Processing
Options
Compile the Design
The Report File
Pin-out file (.pin)
Floorplan Editor
Floorplan Views
Floorplan Editor (Read
Only)
Floorplan Editor (Read
Only)
Floorplan Editor (Editable)
Floorplan Editor (Editable)
Lab2
Project Compilation Recommendations
Project Compilation Summary
Simulation
MAX+PLUS II Simulator
MAX+PLUS II Simulation
Simulation Waveform
Create Waveform Simulation
Stimulus
Grid Control
Draw Stimulus Waveform
Create Clock Waveform
Create Counting Pattern
Grouping Signals and
Set Radix
Save the Waveform Stimulus
File
Create Vector Simulation
Stimulus
Save the Vector Stimulus
File
Select Simulation Stimulus
File
Specify Length of Simulation
Run Functional Simulation
MAX+PLUS II Functional
Simulation
Run Timing Simulation
MAX+PLUS II Timing Simulation
Comparing Different Simulations
Lab3
Project Simulation Recommendations
Project Simulation Summary
Timing Analysis
MAX+PLUS II Timing Analyzer
Project Timing Analysis
Registered Performance
Analysis
Run Registered Performance
Analysis
Tracing Delay Path In
Floorplan Editor
Application of Registered
Performance
Delay Matrix Analysis
Delay Matrix Source and
Destination
Useful Analysis Options
Cut Off I/O Pin Feedback
Run Delay Matrix Analysis
Setup/Hold Matrix Analysis
Run Setup/Hold Matrix
Analysis
Lab4
Timing Analysis Recommendations
Project Timing Analysis
Summary
Device Programming
PPT 슬라이드
Device Adapters
Setting up the Programmer
Programmer
Multi-FLEX Device Configuration
Programmer is ready for
FLEX Chain
JTAG Configuration or
Programming
Programmer is ready for
JTAG Chain
Lab 5
Altera Design Methodology
The Big Picture
Hierarchical Design
Compile
Verify
Back-Annotate Project
Program
Lab6
ALTERA’S SUPPORT COMMITMENT
Appendix I AHDL Examples
Simple AHDL Examples
AHDL Counter
State Machine
Appendix 2 Device Architecture
FLEX 8000 Block Diagram
FLEX 8000 LAB
FLEX 8000 Logic Element
FLEX 10K Block Diagram
FLEX 10K LAB
FLEX 10K Logic Element
FLEX 10K EAB
FLEX 10K EAB
FLEX 10K EAB
FLEX 10K EAB
FLEX 6000 Block Diagram
FLEX 6000 LAB
FLEX 6000 Logic Element
MAX 7000/E/S/A Device
Block Diagram
MAX 7000/E/S/A Logic
Array Block
MAX 7000/E/S/A Macrocell
MAX 9000 Device Block
Diagram
MAX 9000 Logic Array
Block
MAX 9000 Macrocell
Appendix 3 Command-line
Mode
Command-Line Mode
MAX+PLUS in Command-Line
Mode
MAX+PLUS II Command-Line
Mode
MAX+PLUS II Command-Line
Mode
MAX+PLUS II Command-Line
Mode
MAX+PLUS II Command-Line
Mode
Compiling in MAX+PLUS
II
Running the Simulator
Running Register Performance
test
Running the Delay Matrix
Running the Setup/Hold
Matrix
Setacf Utility
Setacf Utility
Changing the device and/or
speed grade
Other assignments
Recommendation
Summary: Command-Line
Command Line Exercises |
작성한 사람:
Jim Connor
프레젠테이션 원본을
다운로드합니다. |
