Compiler Input Files

• Design files

  • MAX+PLUS II
    • Graphics file (.gdf), AHDL file (.tdf), VHDL file (.vhd), Verilog (.v), Wavefrom file (.wdf)
  • 3rd Party EDA Tools
    • EDIF file (.edf)
      • Select Vendor in EDIF Netlist Reader Settings
      • Library Mapping File (.lmf) required for vendors not listed
    • OrCAD file (.sch)

• Assignment and Configuration File (.acf)

  • Controls the Compiler’s synthesis and place & route operations
  • Automatically generated when user enter assignments
  • Automatically updated when user changes assignments or back-annotates project

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