MAX+PLUS II Functional Simulation
Use to verify operation of design
Advantage over Timing Simulation
- Fast compilation
- All nodes are retained and can be simulated
- Outputs are updated without delay
- Most of the time, this makes figuring out cause and effect much easier
Disadvantages
- Logical model only, no logic synthesis
- No delays in simulation
- Oscillations, glitches and other timing related errors do not show up