MAX+PLUS II Timing Simulation

• Used to debug timing related errors

• Advantages over Functional Simulation
  • Simulation of full synthesis result
  • Outputs change after timing delay
    • Detection of oscillations, glitches and other timing related errors are possible

• Disadvantages
  • Longer compilation time
  • Combinatorial logic nodes cannot be simulated
    • Node may be transformed or removed
  • Only “Hard” nodes can be simulated
  • Timing delays make debugging more difficult because cause and effect relationships are harder to locate

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