Timing Analysis Recommendations

• Use Timing Analyzer to locate performance bottleneck

• Use Registered Performance Analysis to determine internal clock frequency performance of the design

• Use Show Only Longest Path Time Restrictions in Delay Matrix to get the longest delay time from input pin to output pin

• Use List Path and Locate in Floorplan Editor to view worst case paths

• Use List Path and Locate to trace through path in design file

• Use assignments and recompile to fine-tune performance

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