FLEX 10K Logic Element
Data 1
Data 2
Data 3
Data 4
ENA
to LAB Local
Interconnect
to
Row, ColumnInterconnects
Carry
Chain
Cascade
Chain
LUT
Clear & Preset
Logic
D
Q
Clock Selection
Mux for Register Packing
Carry in
Cascade
in
Carry
Out
Cascade
Out
LAB Clear/Preset 1
LAB Clear/Preset 2
Chip-Wide Reset
CLRN
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