ALTERA Advanced Course

목차

PPT 슬라이드
Agenda
Altera General-Purpose Logic Devices
Introduction to Altera
Altera Device Terminology
Product Term-Based Building Blocks
Look-Up Table-Based Building Blocks
Which PLD Should I Use?
MAX 7000 Device Technology
MAX 7000(E)(S) Family
MAX 7000(E)(S) Family
Device Part Numbers
Device Block Diagram
PPT 슬라이드
Logic Array Block
MAX 7000E/S/A/B MAX 7000
XOR Functionality
Expanders
Shareable Logic Expanders
Parallel Expanders
Parallel Expanders- Architecture Rules
Parallel Expanders- Architecture Rules
Parallel Expanders- Architecture Rules
PPT 슬라이드
PPT 슬라이드
PPT 슬라이드
Special Features
MAX7000A
MAX7000A
MAX 9000 Family
MAX 9000 Device Block Diagram
MAX 9000 Logic Array Block
MAX 9000 Dedicated Inputs
MAX 9000 Dedicated Inputs
MAX 9000 Macrocell
Register Packing
Use Register Packing as a Last Resort
MAX 9000 I/O Cell
I/O Cell Register
I/O Cell Register Controls
Output Enables
Slew-Rate Control
Design Methodology and Guidelines for MAX 7000 & MAX 9000 Devices
Altera Design Methodology
Recommended Design Guidelines
Design Hierarchically
Evaluate Existing Functions
Evaluate Intellectual Property
Use Dedicated Inputs for Control Signals
Reserve Resources in the Device
Compile Without Assignments Initially
Pin and Logic Cell Assignments
Pin Assignment Guidelines
Control Signals
Assigning Output Enables
Assigning Output Enables
Estimate Fan-In to Assign Output Pins
Outputs Using Parallel Expanders
PPT 슬라이드
PPT 슬라이드
PPT 슬라이드
Assign Wide Buses to Row Pins
Altera Design Methodology
Topics
When Compiler Can’t Find a Fit
Error Message
Resolving Macrocell Usage Issues
Resolving Routing Issues
Logic Synthesis
Multi-Level Synthesis
Multi-Level Synthesis
Synthesis Example
Synthesis Example
Fitter Settings
Custom Fitting
Fitter Settings Dialog Box
Using LCELLs
Alternative to Inserting LCELLs
Using LCELLs - Example
Fitting Enhancement Summary
Still Doesn't Fit?
Altera Design Methodology
Device Timing
PPT 슬라이드
PPT 슬라이드
PPT 슬라이드
MAX+PLUS II Timing Analysis
MAX+PLUS II Compilation
Achieving Performance in MAX devices
Major Contributors to Long Delays
Improving TSU
Improving TCO
PPT 슬라이드
If FMAX Requirements Are Not Achieved...
If FMAX Requirements Are Not Achieved...
If FMAX Requirements Are Not Achieved...
If FMAX Requirements Are Not Achieved...
Reducing Interconnect Delay- MAX 9000
Resolving Performance in MAX Devices
Still Not Enough Performance?
FLEX 8000 Family
FLEX 8000 Block Diagram
FLEX 8000 Dedicated Inputs
FLEX 8000 LAB
FLEX 8000 Logic Element
Architecture Features
Carry Chain
Cascade Chain
Cascade Chain Example
Carry and Cascade Chain Construction
Using Carry Chains in Your Design
Using Cascade Chain
Synthesis Styles & FLEX Features
FLEX 8000 IOE
FLEX 6000
FLEX 6000 Block Diagram
FLEX 6000 Global Nets
FLEX 6000 LAB
FLEX 6000 LAB Control Signals
FLEX 6000 Logic Element
Architecture Features
FLEX Internal Tri-State Emulation
FLEX Internal Tri-State Emulation
LE-to-LE Connection: LAB Interconnect Only
Row Outputs
FLEX 6000 IOE
Designing with FLEX 6000 & FLEX 8000 Devices
Designing with FLEX 6000 & FLEX 8000 Devices
Altera Design Guidelines
Using Global Nets
Pin Assignments
Pin Assignments: Bidirectional I/O Pins
Pin Assignments: Critical Net
Pin Assignments: High Fan-Out Net
Pin Assignments: Wide Bus
Device Timing
Device Timing: Setup & Hold Times
Device Timing: Setup & Hold Times
Device Timing: Setup & Hold Times
Device Timing: Clock-to-Out
Device Timing: Clock-to-Out
Device Timing: Clock Frequency
Device Timing: Clock Frequency
Timing-Driven Compilation
Global Area/Speed Optimization
FLEX 10K Family
FLEX10K family
FLEX 10K Family Block Diagram
Dedicated Inputs, Clocks
FLEX 10K Family LAB
FLEX 10K Family LAB Control Signals
FLEX 10K Family Logic Element
Architecture Features
Register Packing
Register Packing
Carry Chain
Carry Chain
Cascade Chain
I/O Element
EAB
Available RAM in FLEX 10K Family Devices
EAB
Cascading EABs for Memory
FLEX 10K/V/A/B EAB - Single Port
FLEX 10K/V/A/B EAB
FLEX 10KE EAB - Dual Port
10KE EAB
MAX+plus II’s MegaWizard
MegaWizard Manager Output
Memory Elements and Implementation
Use of EAB
Designing with FLEX 10K Family Devices
Designing with FLEX 10K Family Devices
FLEX 10K Family Devices - Usable Gates
Achieving Optimal Utilization
FLEX 10K Family Devices- Performance
Achieving Optimal Performance
In Design
In Design
In Design
In Design
In Design
In Design
In Design
In Design
In Design
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
Device Timing: Setup & Hold Times
In Architecture / MAX+plus II
Device Timing: Clock-to-Output
In Architecture / MAX+plus II
In Architecture / MAX+plus II
Device Timing: Clock Frequency
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
In Architecture / MAX+plus II
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Analyzing and Improving Results
Note - Timing Analyzer
Note - Timing Analyzer
FLEX In-Circuit Reconfigurability (ICR)
FLEX Configuration Overview
Configuration Mediums
Configuration Modes
Configuration Modes
Choosing Appropriate Mode
Multiple FLEX Devices
Configuration Application Notes
Configuration Application Notes, Data Sheets
Configuration Data
Configuration Data
Configuration Reliability
Configuration Pins
Configuration Pins
General Steps of Configuration
General Steps of Configuration
General Steps of Configuration
General Steps of Configuration
Configuration Device Options

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