MAX 7000(E)(S) Family
Features ...
- High-performance, mid-density EPLD standard
- 32 ~ 256 macrocells, 600 ~ 5,000 usable gates
- 5 V MAX 7000(E) devices and 5 V ISP MAX 7000S
- In-System Programmability(ISP) in MAX 7000S
- Built-in JTAG BST circuitry in MAX 7128S or above
- 5 ns pin-to-pin delays with up to 175.4 MHz counter frequency
- PCI-compiliant devices available
- Open-drain output option in MAX 7000S
- Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
- Programmable power-saving mode for a reduction of over 50 % in each macrocell