MAX 9000 Family
Features...
- High performance and high density EPLD
- 320 ~ 560 macrocells, 6,000 ~ 12,000 usable gates
- 5 V ISP via built-in JTAG interface
- Dual-output macrocell for independent use of combinatorial and registered logic
- FastTrack Interconnect
- Input/Output registers on all I/O pins
- 10 ns pin-to-pin delays up to 144 MHz counter frequency
- PCI compliant (-12 speed grade)
- 3.3V or 5 V I/O operation/MultiVolt I/O interface
- Programmable output slew-rate control