I/O Cell Register Controls

VCC

VCC

VCC

CLR [1..0]

ENA[5..0]

CLK[3..0]

OE[7..0]

13

8

4

6

2

CLRN

ENA

D

Q

to Row or Column FastTrack Interconnect

Peripheral Control Bus [12..0]

from Row or Column FastTrack Interconnect

Available Control

Signals for I/O

Registers

• 4 Clocks from Peripheral Control Bus

• 2 Clears from Peripheral Control Bus

• 6 Clock Enables from Peripheral Control Bus

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