PPT 슬라이드

fMAX = 1 / (register clock-to-Q + data delay + register setup + clock skew)
• Register clock-to-Q time (see data book)
• Register setup time (see data book)
• Clock skew - depends on resource used
  • Dedicated Inputs drive global signals & PIA
  • I/O pins drive PIA
• Data delay - depends on
  • Logic delay between registers
  • Proximity of registers

logic

data delay

D

Q

D

Q

clock skew

Device Timing - Clock Frequency

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

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