Major Contributors to Long Delays

• Excessive levels of logic

  • Biggest contributor

• Excessive loading (high fan-out)

  • When a driving signal drives out to more than one LAB, the PIA delay increases by 0.1 ns per additional LAB fan-out
  • The 0.1 ns adder is the same for all devices
  • To minimize the added delay, concentrate the destination macrocells into fewer LABs to minimize the number of LABs that are driven

• Excessive Row/Column interconnect delay

  • Worst-case timing parameters for typical applications
  • tlocal :0.5 ns, trow : 0.9 ns, tcolumn : 0.9 ns

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

그래픽 버전 보기