Device Timing: Clock Frequency

To Obtain Highest Possible Clock Frequency

• In MAX+PLUS II
  • Use Global Nets for Clock Signals
  • Carry Chain Reduces Combinatorial Logic Delay for Arithmetic Functions
  • “Fast” Synthesis Utilizes Carry, Cascade, Speed-Enhancing MAX+PLUS II Options
  • Use Local Routing Assignment Option

• In Design
  • Do Not Also Use Clock Signal for Data
  • Divide Large Blocks of Combinatorial Logic/Delay with Registers (Pipelining)
    • Remember: Combinatorial Logic Divided into 4-Input LUTs = 1 Logic Level
    • “Free” Register after Every LUT

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