목차
PPT 슬라이드
Altera’s
Introduction to VHDL
Course Outline
Course Outline
VHDL Basics
PPT 슬라이드
PPT 슬라이드
VHDL History
Terminology
Behavior Modeling
Structural Modeling
More Terminology
PPT 슬라이드
PPT 슬라이드
PPT 슬라이드
PPT 슬라이드
VHDL Design Units
VHDL Basics
Entity Declaration
Entity : Generic Declaration
Entity : Port Declarations
Architecture
Architecture
PPT 슬라이드
VHDL :
Entity - Architecture
Configuration
Putting it all together
Packages
Packages
Package Example
Libraries
Model Referencing of Library/Package
Example
Libraries
Types defined in
Standard Package
Libraries
Types defined in std_logic_1164 Package
User-Defined
Libraries/Packages
PPT 슬라이드
Section Overview
Using Signals
Assigning values to Signals
Signal used as an interconnect
Signal
Assignments
Concurrent Signal Assignments
Simple Signal Assignments
PPT 슬라이드
PPT 슬라이드
Arithmetic
Function
Operator Overloading
Operator Overloading Function/Package
PPT 슬라이드
PPT 슬라이드
Conditional
Signal Assignments
Selected Signal Assignments
Selected Signal Assignments
Selected
Signal Assignment
VHDL Model - Concurrent Signal Assignments
Explicit
Process Statement
Execution of Process Statement
Multi-Process Statements
VHDL Model
- Multi-Process Architecture
Variable Declarations
Assigning values to Variables
Variable Assignment
PPT 슬라이드
Signal
and Variable Scope
PPT 슬라이드
Sequential Statements
If-Then Statements
If-Then Statements
If-Then Statements
Case Statement
Case Statement
Case Statements
Sequential LOOPS
FOR LOOP using a Variable: 4-bit Left Shifter
FOR LOOP
using a Variable: 4-bit Left Shifter
PPT 슬라이드
VHDL Model
- RTL Modeling
PPT 슬라이드
PPT 슬라이드
LATCH
DFF - clk= '1'
DFF with WAIT statement
DFF - clk’event and
clk= '1'
DFF - rising_edge
DFF with asynchronous clear
How Many Registers?
How Many
Registers?
How Many Registers?
How Many Registers?
How Many Registers?
How Many Registers?
Variable Assignments in Sequential Logic
PPT 슬라이드
PPT 슬라이드
Finite
State Machine (FSM) - State Diagram
Enumerated Data Type
Writing
VHDL Code for FSM
Writing VHDL Code for FSM
FSM VHDL Code - Enumerated
Data Type
FSM VHDL Code - Next State Logic
FSM VHDL Code - Outputs
FSM VHDL
Code - Outputs using a Case
PPT 슬라이드
PPT 슬라이드
Design Hierarchically - Multiple Design Files
Component
Declaration and Instantiation
Component Declaration and Instantiation
Component
Declaration and Instantiation
PPT 슬라이드
Vendor Libraries
Library Altera/LPM
LPMs
LPM Instantiation
LPM Instantiation - lpm_mux
LPM Instantiation - lpm_mult
Benefits
of LPMs
LAB1
LAB2
LAB3
LAB4
LAB5
LAB6 |
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