PPT 슬라이드

VHDL Basics

• Two sets of constructs:

  • Synthesis
  • Simulation

• The VHDL Language is made up of reserved keywords.

• The language is, for the most part, NOT case sensitive.

• VHDL statements are terminated with a ;

• VHDL is white space insensitive. Used for readability.

• Comments in VHDL begin with “--” to EOL

• VHDL models can be written:

  • Behavioral
  • Structural
  • Mixed

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