Signal used as an interconnect

r

t

g

h

qb

Signal Declaration

inside Architecture

• r, t, g, h, and qb are Signals (by default)

• qa is a buried Signal and needs to be

declared

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY simp IS

PORT(r, t, g, h : IN STD_LOGIC;

qb : OUT STD_LOGIC);

END simp;

ARCHITECTURE logic OF simp IS

SIGNAL qa : STD_LOGIC;

BEGIN

qa <= r or t;

qb <= (qa and not(g xor h));

END logic;

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