VHDL Model - Concurrent Signal Assignments

The signal assignments execute in parallel, and therefore the order we list the statements should not affect the outcome

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY cmpl_sig IS

PORT ( a, b, sel : IN STD_LOGIC;

x, y, z : OUT STD_LOGIC;

END cmpl_sig;

ARCHITECTURE logic OF cmpl_sig IS

BEGIN

-- simple signal assignment

x <= (a AND NOT sel) OR (b AND sel);

-- conditional signal assignment

y <= a WHEN sel='0' ELSE

-- selected signal assignment

WITH sel SELECT

z <= a WHEN '0',

b WHEN '1',

'0' WHEN OTHERS;

END logic;