VHDL Model - Multi-Process Architecture

• The Process statements execute in parallel and

therefore, the order in which we list the statements

should have no affect on the outcome

• Within a Process,

the statements are

executed sequentially

case_label: PROCESS(a, b, c, d, sel)

BEGIN

CASE sel IS

WHEN "00" =>

z <= a;

WHEN "01" =>

z <= b;

WHEN "10" =>

z <= c;

WHEN "11" =>

z <= d;

WHEN OTHERS =>

z <= '0';

END CASE;

END PROCESS case_label;

END logic;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY if_case IS

PORT ( a, b, c, d : IN STD_LOGIC;

sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

y, z : OUT STD_LOGIC);

END if_case;

ARCHITECTURE logic OF if_case IS

BEGIN

if_label: PROCESS(a, b, c, d, sel)

BEGIN

IF sel="00" THEN

y <= a;

ELSIF sel="01" THEN

y <= b;

ELSIF sel="10" THEN

y <= c;

ELSE

y <= d;

END IF;

END PROCESS if_label;

• Signal Assignments can also be

inside Process statements.

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