This section describes the files you need to translate, map, place, and route your design using the XSI and Synopsys tools.
| File | Description | FPGA Compiler or Design Compiler |
|---|---|---|
| design_name.script | The design_name.script file is user-created and contains the commands for Synopsys FPGA Compiler or Design Compiler. These commands specify the operating conditions, the name and format of the design file, and synthesis directives. Script files can have extensions other than .script. | Both |
| design_name.v | The .v extension indicates the Verilog HDL format. | Both |
| design_name.vhd | The .vhd extension indicates the VHDL format. | Both |
| .synopsys_dc.setup | The .synopsys_dc.setup file is the startup file for the Synopsys synthesis tools. It must reside in your home directory or working directory. | Both |
| XC4000e.sdb | The XC4000e.sdb file contains XC4000E schematic symbols for Synopsys. | Both |
| XC4000ex.sdb | The XC4000ex.sdb file contains XC4000EX schematic symbols for Synopsys. | Both |
| XC4000xv.sdb | The XC4000xv.sdb file contains XC4000XV schematic symbols for Synopsys. | Both |
| XC5200.sdb | The XC5200.sdb file contains XC5200 schematic symbols for Synopsys. | Both |
| XC3000a.sdb | The XC3000a.sdb file contains XC3000A schematic symbols for Synopsys. | Both |
| .syn | SYN files define synthetic library elements for Synopsys DesignWare software. These files support XC4000E/L/EX/XL/XLA/XV and XC5200 devices. | Both |
| .sim | VSS simulation uses SIM files. | Both |
| design_name.sxnf | The design_name.sxnf file is the synthesized design generated by the Synopsys synthesis tools. | FPGA Compiler |
| design_name.sedif | The design_name.sedif file is the synthesized design generated by the Synopsys synthesis tools using the EDIF syntax. | Design Compiler |
| design_name.ncf | DC2NCF creates the design_name.ncf file. DC2NCF converts timing constraints applied to your design in the Synopsys environment to equivalent constraints that control the Xilinx place and route process. | Both |
| design_name.ngo | EDIF2NGD or XNF2NGD create the design_name.ngo file, which contains a logical description of your design in terms of its original components and hierarchy. | Both |
| design_name.ngd | The NGDBuild program generates the design_name.ngd file, a binary file containing a logical description of your design in terms of both its original components and hierarchy, and the NGD primitives to which your design is reduced. | Both |
| design_name.ncd | The MAP program generates the design_name.ncd file, a physical description of your design in terms of the components in the target Xilinx device. | Both |
| design_routed.ncd | The design_routed.ncd file, generated by PAR, is your placed and routed design. | Both |
| design_name.nga | NGDAnno generates the design_name.nga file, a back-annotated NGD file. | Both |
| design_name.vhd | This file is the VHDL timing simulation model created by the NGD2VHDL program. | Both |
| design_name.sdf | This file is the timing back-annotation file created by the NGD2VHDL program. | Both |
