Glossary...

 

XILINX Glossary

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

A
Aliases
asynchronous debugging
attribute
AutoRoute

B
BIT file
bitstream (BIT file)
block
bottom-up design
BUFT
byte-wide PROM

C
CCLK pin
CLKI pin
CLKO pin
clock input path
clock skew
component
constraint
Constraints Editor
critical path

D
D/P (XC3000) pin
daisy chain
DC2NCF
debugging
DIN pin
DONE (Spartan/XC4000/XC5200)
downloading

E
EDIF
EXORmacs (Motorola)
external clock

F
fitting

G
GND pin
group
guide file
guided mapping

H
HDL
HEX
hold time

I
Implementation Tools
INIT pin
instance
internal XChecker clock
IOB (input/output block)

L
.ll
LCA file
LCA2NCD
loading direction
locking
LogiBLOX
Logic Block Editor
logic icon
logic synthesis

M
macro
mapping
MCS file
MCS-86 (Intel)
MDF file
MFP File
MRP file

N
NCD file
NCF file
net
NGA file
NGC File
NGD file
NGD2EDIF
NGD2VER
NGD2VHDL
NGDAnno
NGDBuild
NGM file
number of clock cycles

O
one-to-one logic
optimization

P
pad
PAR (Place and Route)
path delay
PCF file
physical Design Rule Check (DRC)
physical macro
pin
pinwires
place effort
placer
placing
primitive
probing
PROG pin
programming
PROM
PROM file

R
RBT file
RD pin
readback
route effort
route-through
router
routing
RPM
RST pin
RT pin

S
schematic
script
SDF
serial PROM
setup time
snapshot
states
static timing analysis
status bar
synchronous debugging
synthesis

T
TCK pin
TDI pin
TEKHEX (Tektronix)
timing
timing constraints
TMS pin
toolbar
toolbox
top-down design
TRCE
TRIG pin
trigger
TTY
TWR file

U
UCF file
universal interconnect matrix (UIM)

V
VCC pin
verification
Verilog
VHDL

W
waveform
WIR file
wire
workspace

 

A

Aliases
Alias³ª Signal GrouppingÀ» ÀǹÌÇϸç, °¢ Node (Signal) ¸¦ GrouppingÇÏ¿© ProbingÇÒ¶§ À¯¿ëÇÏ°Ô »ç¿ëµÈ´Ù.

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asynchronous debugging
ºñµ¿±âÀûÀÎ µð¹ö±ëÀº »ç¿ëÀÚ°¡ ½Ã½ºÅÛ Å¬·°À» Á¦¾îÇÏÁö ¾Ê°í µ¥ÀÌÅ͸¦ Àâ´Â FPGA µð¹ö±ë ¸ðµåÀÌ´Ù.

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Attribute
FPGA ¼³°èȸ·Î»ó¿¡ ¹èÄ¡,¹è¼± Áöħ, Compile, Symbol name µî ȸ·ÎÁ¤º¸¸¦ SymbolÀ̳ª Net¿¡ ³ªÅ¸³¾ ¼ö ÀÖ´Â ¼±¾ð¹®.

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AutoRoute
ȸ·Î»óÀÇ ÀÚµ¿ ¹è¼±.

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B

BIT file
BITÆÄÀÏÀº bitstreamÆÄÀÏ°ú µ¿ÀǾîÀÌ´Ù.

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bitstream (BIT file)
bitstream ÆÄÀÏÀº µð¹ÙÀ̽º»óÀÇ À§Ä¡ Á¤º¸, Áï CLB, IOB, TBUF, pinÀÇ ÇÒ´ç°ú ¶ó¿ìÆÿä¼Ò¸¦ Æ÷ÇÔÇÑ µ¥ÀÌÅÍÀÇ È帧ÀÌ´Ù.  bitstreamÀº ¶ÇÇÑ readbackµ¿¾È µð¹ÙÀ̽º¿¡ ÀÇÇØ º¸³»¾îÁö´Â ³í¸®ÀûÀÎ »óÅ·Πä¿öÁø ÅÖºó placeholderµéµµ Æ÷ÇÔÇÑ´Ù.  ´ÜÁö flip-flops, RAMs, CLB Ãâ·Â °°Àº ¸Þ¸ð¸® ¿ä¼ÒµéÀÌ ÀÌ·¯ÇÑ placeholder¿¡ ¹èÄ¡µÈ´Ù.  ¿Ö³ÄÇϸé, ±× ³»¿ëµéÀÌ ¾î´À ÇÑ »óÅ¿¡¼­ ´Ù¸¥ »óÅ·Πº¯ÇÏ´Â °Í °°±â ¶§¹®ÀÌ´Ù.  bitstreamÀÌ µð¹ÙÀ̽º¿¡ ´Ù¿î·ÎµåµÉ¶§ µð¹ÙÀ̽ºÀÇ ³í¸®È¸·Î¸¦ ¼³Á¤ÇÏ°í µð¹ÙÀ̽º¸¦ ÇÁ·Î±×·¥Çؼ­ µð¹ÙÀ̽ºÀÇ »óÅ°¡ ´Ù½Ã ¿ªÀ¸·Î ÀÐÇôÁú ¼ö ÀÖ´Ù.  bitstream ÆÄÀÏÀº .bit È®ÀåÀÚ¸¦ °¡Áø´Ù.

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Block
ÇÑ °³³ª ±×ÀÌ»óÀÇ Logic FunctionÀÌ °áÇÕµÈ ´ÜÀ§.

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bottom-up design
Bottom-up designÀº °¡Àå ÃÖÇÏÀ§ÀÇ È¸·ÎºÎÅÍ ¼³°èÇϴ ȸ·Î ¼³°è ±â¹ýÁßÀÇ ÇϳªÀÌ´Ù.  ÇÏÀ§ºÎºÐ ¼³°èÈÄ »óÀ§ ºÎºÐÀ» ¼³°èÇÏ¿©¸¸ÀÌ È¸·Î ¼³°è¸¦ ¿Ï¼ºÇÒ ¼ö ÀÖ´Ù.  ÀÌ ¹æ¹ýÀº ÀüÅëÀûÀ¸·Î schematic ¼³°è±â¹ý¿¡¼­ »ç¿ëµÈ´Ù.

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BUFT
BUFT´Â Æ®¶óÀ̽ºÅ×ÀÌÆ® ¹öÆÛÀÌ´Ù.

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byte-wide PROM
byte-wide PROM´Â Çѹø¿¡ ÇÑ ¹ÙÀÌÆ® µ¥ÀÌÅ͸¦ Á¦°øÇÏ´Â PROMÀÌ´Ù.  FPGAÀÇ µ¥ÀÌÅ͸¦ º´·Ä·Î ÇÁ·Î±×·¥ÇÒ¶§ »ç¿ëµÈ´Ù.

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C

CCLK pin
CCLK ÇÉÀº ´Ù¿î·Îµåµ¿¾È µ¥ÀÌÅÍ Àü¼Ò¿¡ ÇÊ¿äÇÑ clockÀ» Çϳª ȤÀº ¿©·¯°³ÀÇ ¿¬°áµÈ µð¹ÙÀ̽º¿¡°Ô ÁÖ´Â XChecker ÄÉÀ̺íÀÇ ÇÉÀÌ´Ù.

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CLKI pin
XChecker clock ÀÔ·Â ÇÉÀº systemÀÇ clockÀ» XChecker ÄÉÀÌºí¿¡ ¿¬°áÇÑ´Ù.  ÀÌ clockÀÇ ÁÖÆļö´Â 120 kHz¿¡¼­ 10 MHz ¹üÀ§¿¡ ÀÖ¾î¾ß¸¸ ÇÑ´Ù.  CLKIÇÉ¿¡ ½Ã½ºÅÛ clockÀ» ¿¬°áÇÏ´Â °ÍÀº Hardware Debugger°¡ ½Ã½ºÅÛ clockÀ» Á¦¾îÇؼ­ ȸ·Î°¡ ¾Ë°í ÀÖ´Â »óÅÂÀΰ¡¸¦ °Ë»çÇÑ´Ù.  ¸¸¾à clock Ãâó°¡ ¿ÜºÎÀ̸é clock ½ÅÈ£´Â CLKIÇÉ¿¡ ¿¬°áµÈ´Ù.  ³»ºÎÀ̸é clock ½ÅÈ£´Â XChecker ÄÉÀÌºí¿¡ ÀÇÇØ ¹ß»ýµÈ´Ù.

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CLKO pin
XChecker ÄÉÀ̺í Ãâ·Â ÇÉÀº ¸ñÀû ½Ã½ºÅÛ clockÀÇ ¸ñÀûÁö¿¡ ¿¬°áµÈ´Ù.  ½Ã½ºÅÛ clokc¿¡ CLKOÇÉÀ» ¿¬°áÇÏ´Â °ÍÀº Hardware Debugger°¡ ½Ã½ºÅÛ clockÀ» Á¦¾îÇؼ­ ȸ·Î°¡ ¾Ë°í ÀÖ´Â »óÅÂÀÎÁö¸¦ °Ë»çÇÑ´Ù.

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clock input path
clock ÀÔ·Â °æ·Î´Â ĨÀÇ ÀÔ·ÂÀ̳ª flip-flop, latch, RAMÀÇ Ãâ·Â Áß ¾î´À Çϳª¿¡¼­ ½ÃÀÛÇÏ°í flip-flipÀ̳ª latchÀÇ enable»ó¿¡¼­ ¾î¶°ÇÑ clock ÇÉ¿¡¼­ ³¡³­´Ù.  clock ÀÔ·Â °æ·Î ½Ã°£Àº flip-flop clock ÀԷ¿¡ µµ´ÞÇÒ ½ÅÈ£¿¡ ÇÊ¿äÇÑ ÃÖ´ë ½Ã°£ÀÌ´Ù.  Clock ÀÔ·Â ÇÉ °æ·Î´Â ½Ã½ºÅÛ ´Ü°èÀÇ È¸·Îµµ ½Ã°£À» °áÁ¤Çϴµ¥ »ç¿ëµÈ´Ù.

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clock skew
Clock skew´Â clock ½ÅÈ£°¡ ¿øõ flip-flop¿¡ µµ´ÞÇÏ´Â ½Ã°£°ú ÃÖÁ¾ flip-flop ¿¡ µµ´ÞÇÏ´Â ½Ã°£ÀÇ Â÷ÀÌÀÌ´Ù.  ÀÌ°ÍÀº ¶ÇÇÑ clock Áö¿¬À¸·Î ¾ð±ÞµÈ´Ù.

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Component
ȸ·Îµµ»ó¿¡ ¹èÄ¡µÉ ¼ö ÀÖ´Â LogicÀÇ ±âº» ±¸¼º¿ä¼Ò·Î System Library¿¡ Æ÷ÇԵǾîÀÖ´Ù.

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Constraint
Compile°úÁ¤ÀÇ ÁöħÀ¸·Î, Routing, Timing, Area, Mapping, Placeµî ¸î°¡Áö°¡ÀÖ´Ù.  Attribute¸¦ »ç¿ëÇÏ¿© CLB³»ºÎ¿¡ LogicÀ» È¿À²ÀûÀ¸·Î ¹èÄ¡ÇÒ ¼ö ÀÖ°í, Chip»ó¿¡ CLBÀÇ ¹èÄ¡¸¦ ¼±Á¤ÇÏ¿© Flip-Flops»çÀÌ¿¡ Delay¸¦ ÃÖ¼ÒÈ­ÇÒ ¼ö ÀÖ´Ù.  ±×·¯³ª, ȸ·Î»ó Constraint¸¦ ºÎ¿©ÇÑ Logic¿¡ ´ëÇؼ­´Â Compile (PAR) °úÁ¤¿¡¼­ À§Ä¡Á¤º¸¸¦ ChangeÇÏ¿© ¼öÇàÇÏÁö´Â¾Ê´Â´Ù.  CLBµéÀº Çà°ú¿­¿¡ ¹è¿­µÇ¾îÁø´Ù.  DeviceÀÇ Çà¿¡ ¹èÄ¡µÇ¾îÁö´Â °ÍÀÌ DesignÀÇ ¼º´É°ú SizeÃø¸é¿¡¼­ º¼¶§, ÃÖ´ëÀÇ ¹èÄ¡°á°ú¸¦ ´Þ¼ºÇÏ´Â °ÍÀÌ´Ù.

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Constraints Editor
Constraints Editor´Â Design»ó »õ·Î¿î Constraint¸¦ ºÎ¿©Çϰųª À̹ÌÁ¸ÀçÇÏ´Â Constraint¸¦ Delete ¹× ModifyÇÒ ¼ö ÀÖ´Â GUI (Graphical User Interface)°¡ ÀÖ´Ù.

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critical path
critical path´Â ȸ·ÎÀÇ ¼Óµµ¸¦ Á¦ÇÑÇÏ´Â Á¶ÇÕȸ·ÎÀÇ ºÎºÐÀÇ ½ÅÈ£ÀÌ´Ù.  ÀúÀå ¿ä¼Ò´Â ÀÔÃâ·Â Æе带 Æ÷ÇÔÇÒÁöµµ ¸ð¸£´Â critical path ¸¦ ½ÃÀÛÇÏ°í ³¡³½´Ù.

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D

D/P (XC3000) pin
ÀÌ°ÍÀº µÎ°¡Áö ±â´ÉÀÇ ÇÉÀÌ´Ù.  ÀÔ·ÂÀ¸·Î½á´Â ÇÁ·Î±×·¥µÈ µð¹ÙÀ̽ºÀÇ Àç ÇÁ·Î±×·¥À» ÃʱâÈ­ÇÑ´Ù.  Ãâ·ÂÀ¸·Î¼­´Â ÇÁ·Î±×·¥¹ÖÀÇ ÁøÇàÀÌ ¿Ï·áµÇ¾úÀ½À» Ç¥½ÃÇÑ´Ù.

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daisy chain
daisy chainÀº Çϳª ÀÌ»óÀÇ bitstreamÀ» ¿¬°áÇÑ °ÍÀÌ´Ù.  PROMÀº daisy chain board¿¡ ¿¬°áµÈ ¿©·¯°³ÀÇ FPGA¸¦ ÇÁ·Î±×·¥Çϴµ¥ »ç¿ëµÉ ¼ö ÀÖ´Ù.

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DC2NCF
DC2NCF (design constraints to netlist constraints file)À» ÀǹÌÇϸç, Synopsys DC file¿¡¼­ NCF (Netlist Constraints File) ·Î º¯È¯ÇÏ¿©ÁÖ´Â UtilityÀÌ´Ù.  DC FileÀº constraint designÀ» ÇÒ ¼öÀÖ´Â Synopsys Setup fileÀÌ´Ù.

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debugging
DebuggingÀº µð¹ÙÀ̽º°¡ circuit¿¡¼­ Á¤»óÀûÀ¸·Î µ¿ÀÛÇÏ´ÂÁö¸¦ È®ÀÎÇϱâ À§ÇØ ÇÁ·Î±×·¥µÈ µð¹ÙÀ̽ºÀÇ »óŸ¦ °Ë»çÇϰųª ´Ù½Ã ÀоîµéÀÌ´Â °úÁ¤ÀÌ´Ù.

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DIN pin
FPGA¿¡¼­ DINÇÉÀº Á÷·Ä ¸ðµå¿¡¼­ bitstreamÀ» ¹Þ¾ÆµéÀδÙ.  XChecker cable»ó¿¡¼­ bitstream µ¥ÀÌÅ͸¦ Á¦°øÇÏ°í ¸ñÀû FPGAÀÇ DINÇÉ¿¡ ¿¬°áÇÑ´Ù.

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DONE (Spartan/XC4000/XC5200) pin
ÀÌ°ÍÀº µÎ°¡Áö ±â´ÉÀÇ ÇÉÀÌ´Ù.  ÀÔ·ÂÀ¸·Î½á´Â Àüü ȸ·Î ½ÃÀÛÀ» Áö¿¬½ÃÅ°°Å³ª Ãâ·ÂÇÉÀÌ °¡´ÉÇØÁöµµ·Ï ÇÁ·Î±×·¥µÉ ¼ö ÀÖ´Ù.  Ãâ·ÂÀ¸·Î½á´Â ÇÁ·Î±×·¥¹ÖÀÇ ÁøÇàÀÌ ¿Ï·áµÇ¾úÀ½À» Ç¥½ÃÇÑ´Ù.  ÁÖÀÇ:Virtex µð¹ÙÀ̽º¿¡¼­´Â DONE_CFGÀ¸·Î ¸íĪµÈ´Ù.

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downloading
DownloadingÀº µð¹ÙÀ̽º¿¡ bitstream µ¥ÀÌÅ͸¦ º¸³¿À¸·Î½á µð¹ÙÀ̽º¸¦ ÇÁ·Î±×·¥¹ÖÇϴ ó¸®ÀÌ´Ù.

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E

EDIF
EDIF´Â ȸ·ÎÀÇ netlist¸¦ ÁöÁ¤ÇϱâÀ§ÇØ »ê¾÷ Ç¥ÁØ ÆÄÀÏÀÎ Electronic Data Interchange FormatÀÇ ¾àÀÚÀÌ´Ù.  ÀÌ°ÍÀº third-partyÀÇ È¸·Î¼³°è¿ë Åø¿¡ ÀÇÇØ »ý¼ºµÈ´Ù.

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EXORmacs (Motorola)
Xilinx Åø¿¡¼­ Á¦°øµÇ´Â PROM Çü½ÄÀÌ´Ù.  ÃÖ´ë ¹øÁö´Â 16,777,216ÀÌ´Ù.  ÀÌ Çü½ÄÀº ÃÖ´ë (8 x 16,777,216) = 134,217,728 bitsÀÇ PROM ÆÄÀÏÀ» Áö¿øÇÑ´Ù.

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external clock
external clockÀº µ¿±â½Ä ¸ðµå debuggingµ¿¾È ¸ñÀû board·ÎºÎÅÍ XChecker°¡ »ç¿ëÇÏ´Â ½Ã½ºÅÛ clockÀÌ´Ù.  external clockÀ» »ç¿ëÇϱâÀ§Çؼ­ ½Ã½ºÅÛ clockÀ» CLKIÇÉÀ» »ç¿ëÇÏ´Â XChecker cable¿¡ ¿¬°áÇÏ°í CLKOÇÉÀ» »ç¿ëÇÏ´Â FPGA µð¹ÙÀ̽º¿¡ XChecker ClockÀ» ¿¬°áÇ϶ó.

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F

fitting
FittingÀº CPLD¿¡ ȸ·Îµµ·ÎºÎÅÍ ¹°¸®ÀûÀÎ macrocell À§Ä¡¿¡ ȸ·Î¸¦ ³õ´Â ó¸®ÀÌ´Ù.  RoutingÀº ¸ðµç ȸ·Î½ÅÈ£°¡ ¿¬°á°¡´ÉÇÑ UIM ±¸Á¶¶§¹®¿¡ ÀÚµ¿ÀûÀ¸·Î ¼öÇàµÈ´Ù.

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G

GND pin
GNDÇÉÀº ground ÇÉÀÌ´Ù.

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group
group Àº bus¸¦ Çü¼ºÇÏ´Â °øÅë½ÅÈ£ÀÇ ÁýÇÕÀÌ´Ù.  counterÀÇ °æ¿ì ¿¹¸¦µé¾î ´Ù¸¥ ½ÅÈ£µéÀÌ alias, groupÀ» Çü¼ºÇϱâÀ§ÇØ ¹­ÀÏ ¼öÀÖ´Â ½ÇÁúÀûÀÎ counter °ªÀ» »ý¼ºÇÑ´Ù.

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guide file
guide fileÀº ´ÙÀ½¿¡ À̾îÁö´Â place, route ȤÀº fitting °úÁ¤¿¡ »ç¿ëµÉ FPGA´Â ÀÌ¹Ì place and route°¡ µÇ°í CPLD´Â ÀÌ¹Ì fittingµÈ ÀÌÀüÀÇ ÆÄÀÏÀÌ´Ù.

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Guided mapping
MAP°úÁ¤¿¡¼­ »ý¼ºµÈ NCD file¿¡ "guide"¶õ OptionÀ¸·Î »ç¿ëµÇ¾îÁø´Ù.  Guide fileÀº ±â¹èÄ¡ ¹× ¹è¼±ÀÇ Á¤º¸¸¦ °¡¸®Å²´Ù.

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H

HDL
HDLÀº Hardware Description LanguageÀÇ ¾à¾îÀÌ´Ù.  ¿äÁò °¡Àå º¸ÆíÀûÀÎ HDLÀº Verilog¿Í VHDLÀÌ »ç¿ëµÈ´Ù.  Ãß»óÀûÀÎ »óÀ§ ´Ü°è ±â¹ýÀ» »ç¿ëÇÏ¿© technology¿¡ µ¶¸³ÀûÀ¸·Î ȸ·Î¸¦ ±â¼úÇÑ´Ù.

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HEX
HEX´Â HEXÇü½Ä¿¡¼­ PROM µ¥ÀÌÅÍÀÇ ´Ü¼øÇÑ textÀÌ´Ù.  Á¦ÇѾø´Â µ¥ÀÌÅ;çÀ» °¡Áø´Ù.

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hold time
Hold timeÀº latch ȤÀº flip-flopÀÇ µ¥ÀÌÅÍ ÀÔ·ÂÀÌ ¿Ã¹Ù¸£°Ô °ªÀ» À¯ÁöÇϱâ À§ÇØ ¾ÈÀüÇÑ »óŸ¦ °¡Áú ¼ö ÀÖ´Â clock event ±â°£ÀÌ´Ù.

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I

Implementation Tools
Xilinx Design Compile Tool·Î Á¦°øµÇ¾îÁö¸ç, Tool¿¡´Â NGDBuild, MAP, PAR, AGDAnno, TRCE, NGD2 º¯È¯ Tool, BitGen, PROMGen, EPICÀÌ ÀÖ´Ù.

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INIT pin
INIT ÇÉÀº Àü¿øÀÌ ÄÑÁøÈÄ µð¹ÙÀ̽º°¡ ÇÁ·Î±×·¡¹Ö µ¥ÀÌÅ͸¦ ¹ÞÀ» Áغñ°¡ µÉ¶§ Ç¥½ÃÇÏ´Â µð¹ÙÀ̽º ÇÉÀÌ´Ù.

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instance
instance´Â ȸ·Î¿¡¼­ ȤÀº netlist¿¡¼­ ÁöÁ¤ÇÑ gate³ª °èÃþÀûÀÎ ¿ä¼ÒÀÌ´Ù.  "symbol" ¿ë¾î´Â schematic¿¡¼­ Á¾Á¾ instance¸¦ ¹¦»çÇÑ´Ù.  Instance´Â ÇÉ°ú net¿¡ ÀÇÇØ »óÈ£ ¿¬°áµÈ´Ù.  instance¿¡¼­ net ¿¬°á¼±À» ÅëÇÑ port°¡ ÇÉÀÌ´Ù.  °¡Àå ÃÖÇÏÀ§ÀÇ ¿ä¼Ò·Î ÆîÃÄÁø ȸ·Î´Â ±âÃÊÀûÀÎ instance¸¦ »ç¿ëÇÑ°ÍÀ¸·Î ±â¼úµÈ´Ù.

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internal XChecker clock
internal XChecker clockÀº XCheckerÀÇ ³»ºÎÀÌ°í XChecker CLKO pin¿¡ ÀÇÇØ debugµÉ µð¹ÙÀ̽º¿¡ Àû¿ëµÉ ¼öÀÖ´Ù.

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IOB (input/output block)
IOB FPGA µð¹ÙÀ̽ºÀÇ ÀÔÃâ·Â ±â´ÉÀ» ±¸ÇöÇÏ´Â ±âº»Àû ¿ä¼ÒÀÇ ÁýÇÕÀÌ´Ù.

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L

.ll file
.ll ÆÄÀÏÀº latches, flip-flops, IOBÀÇ ÀÔÃâ·Â µîÀÇ ÀúÀå ¿ä¼ÒÀÇ bitstreamÀ§Ä¡¸¦ Ç¥½ÃÇϴ ȸ·Î ¹èÄ¡ ÆÄÀÏÀÌ´Ù.  Hardware Debugger´Â ÀÌ ÆÄÀÏÀÇ ½ÅÈ£ °ªÀ» readback bitstream¾È¿¡ ³õ±âÀ§ÇØ »ç¿ëÇÑ´Ù.

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LCA file
LCA fileÀºXilinxÀÇ ÀÌÀü Software (XACT)ÀÇ Mapping °á°úÀÇ fileÀÌ´Ù.

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LCA2NCD
LCA2NCD´Â LCA file¿¡¼­ NCD file·Î º¯È¯ÇÏ¿©ÁÖ´Â UtilityÀÌ´Ù.  NCD fileÀº LCA2NCD¿¡¼­ »ý¼ºµÈ ¹èÄ¡, ¹è¼±ÀÌ ¿Ï·áµÈ file·Î EPIC¿¡¼­ º¼ ¼ö ÀÖÀ¸¸ç, Timing Analyzer ¹× Back-AnnotationÀÌ °¡´ÉÇÏ´Ù.

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loading direction
Loading directionÀº PROM¿¡ ÀúÀåµÉ µ¥ÀÌÅÍ ÁÖ¼ÒÀÇ ¹æÇâÀÌ´Ù.  Up direction¿¡¼­ µ¥ÀÌÅÍ´Â ¿À¸§Â÷¼øÀ¸·Î ÀúÀåµÈ´Ù.  Down direction¿¡¼­ µ¥ÀÌÅÍ´Â ³»¸²Â÷¼øÀ¸·Î ÀúÀåµÈ´Ù.

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Locking
Lock placement´Â µðÀÚÀÎ»ó¿¡ constraint·Î ¹èÄ¡µÈ ¸ðµç component¸¦ »ç¿ëÇϸç, ¿©±â¼­ LockingÀÌ Àû¿ëµÈ component´Â Unplace, Move, Delete ÇÒ ¼ö ¾ø´Ù.

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LogiBLOX
Counter, Shift Register, Multiplexerµî°ú °°Àº High level MuduleÀ» ¸¸µé¾îÁÖ´Â Xilinx Design ToolÀÌ´Ù.

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Logic Block Editor
Logic Block Editor´Â »ç¿ëÇÒ chip °è¿­À» ¼±Á¤ÇÑ ÈÄ ±× ³»ºÎ ·ÎÁ÷ µðÀÚÀÎÀ» ÇÒ ¶§ ÀÌ¿ëµÈ´Ù.  Edit Block command´Â Logic Block Editor¿¡¼­ ½ÃÀÛÇÒ ¼ö ÀÖ´Ù.

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logic icon
logic iconÀº flip-flop, buffer, registerµîÀÇ È¸·Î ¿øõÀÇ ±×¸²ÀûÀΠǥÇöÀÌ´Ù.

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logic synthesis
logic synthesis´Â ÀϹÝÀûÀ¸·Î Verilog, VHDL ȸ·ÎÀÇ »óÀ§ ´Ü°è ±â¼ú·ÎºÎÅÍ ½ÃÀÛÇϴ ó¸®ÀÌ°í ±âº»¿ä¼Ò¸¦ Æ÷ÇÔÇÑ ¶óÀ̺귯¸®¸¦ »ç¿ëÇÑ ÇÏÀ§ ´Ü°è ±â¼úÀ» »ý¼ºÇϴ ó¸®ÀÌ´Ù.

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M

Macro
Macro¶õ Component°£, Áï Primitive cells, flip-flops, latchsµé°£ÀÇ net·Î ±¸¼ºµÇ¾îÁ® High level functionÀÌ ±¸ÇöµÈ °ÍÀ» ÀǹÌÇϸç Adder, subtractor, dividerÀÇ ¿¹¸¦ µé ¼ö ÀÖ´Ù.  ¶ÇÇÑ Macro´Â Soft macro¿Í RPMÀ¸·Î ³ª´­ ¼ö ÀÖ´Ù.  Macro´Â unplaced & unrouted, partially PAR or fully PARÀÌ °¡´ÉÇÏ´Ù.

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mapping
MappingÀº µð¹ÙÀ̽º¿¡ ȸ·Î ±â´ÉÀ» ½ÇÁúÀûÀ¸·Î ±¸ÇöÇϴ ƯÁ¤ÇÑ ¹°¸®Àû ¿ä¼Ò¿¡ ȸ·ÎÀÇ ³í¸® ¿ä¼Ò¸¦ ÇÒ´çÇÏ´Â °úÁ¤ÀÌ´Ù.

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MCS file
MCS fileÀº PROMGen ÇÁ·Î±×·¥¿¡¼­ Intel MCS-86 Hex formatÀ¸·Î »ý¼ºµÇ¸ç, ÀϹÝÀûÀÎ PROM HEX formatÀÌ´Ù.

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MCS-86 (Intel)
MCS-86Àº XilinxÅø¿¡¼­ Áö¿øµÇ´Â PROM Çü½ÄÀÌ´Ù.  ÃÖ´ë ÁÖ¼Ò´Â 1,048,576ÀÌ´Ù.  ÀÌ Çü½ÄÀº ÃÖ´ë (8 x 1,048,576) = 8,388,608 bitÀÇ PROM ÆÄÀÏÀ» Áö¿øÇÑ´Ù.

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MDF file
MDF fileÀº ´ÙÀÚÀÎÀÌ MappingµÈ ÈÄ LogicÀÌ ¾î¶»°Ô ºÐ¹èµÇ¾ú´ÂÁö ¼³¸íµÈ FileÀ̸ç, Xilinx software¿¡¼­ guide mapping optionÀ¸·Î »ç¿ëµÈ´Ù.

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MFP File
MFP fileÀº ¼³°èÀÚÀÇ Floorplan´ë·Î µðÀÚÀλóÀÇ ·ÎÁ÷ ¹èÄ¡, Mapping control, Floorplanner¿¡ ÀÇÇØ »ý¼ºµÈ´Ù.

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MRP file
Mapping°úÁ¤ ÈÄ »ý¼ºµÇ´Â MRP fileÀº Mapping°úÁ¤ÀÇ Á¤º¸°¡ ASCII file·Î ÀúÀåµÈ´Ù.

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N

NCD file
NCD (Netlist circuit discription) fileÀº Map, LCA2NCD, PAR, EPIC °úÁ¤ ÈÄ »ý¼ºµÈ Design fileÀ̸ç, flat physical design databaseÀ̳ª, PAR°úÁ¤ÀÌ ¼öÇàµÈ°Í°ú ¾Æ´Ñ °ÍÀÌ ÀÖ´Ù.

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NCF file
NCF fileÀº DCN2NCF programÀ̳ª synthesis vendor toolset¿¡¼­ ¸¸µé¾îÁö¸ç, Toolset¾ÈÀÇ constraint°¡ Æ÷ÇÔÇÑ´Ù.  EDIF2NGD³ª XNF2NGD°¡ NCF file³»ÀÇ constraint¸¦ readÇÏ°í, NGO file¿¡ constraint¸¦ addÇÒ ¼ö ÀÖ´Ù.

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net
netÀº µÎ°³ ¶Ç´Â ±× ÀÌ»óÀÇ symbolµéÀÇ ÇɵéÀ» ¿¬°áÇÏ´Â logical connectionÀ» ÀǹÌÇϴµ¥ routing°úÁ¤À» ÅëÇÏ¿© wire¶ó ºÒ¸®´Â FPGA»óÀÇ ½ÇÁ¦Àû °á¼±À¸·Î º¯È¯µÈ´Ù.

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NGA file
NGA (native generic annotated) ÆÄÀÏÀº NGDAnno ½ÇÇà¿¡¼­ ¹ß»ýµÈ Ãâ·ÂÀÌ´Ù.  NGA ÆÄÀÏÀº ÀûÀýÇÑ NGD2 ¹ø¿ª ÇÁ·Î±×·¥¿¡ À̾îÁö´Â ÀÔ·ÂÀÌ´Ù.

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NGC File
µðÀÚÀλóÀÇ Module´ÜÀ§ÀÇ compileµÈ Binary fileÀ̸ç, NGDBuild program¿¡ ÀÇÇØ EIDF³ª XNF file¾øÀ̵µ Á÷Á¢ ReadÇÒ ¼ö ÀÖ´Ù.  HDL design FlowÀÇ ¿¹¸¦ µé¸é, LogiBLOX programÀº °¢ Module´ç NGC fileÀ» »ý¼ºÇØ »ç¿ëÇÑ´Ù.

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NGD file
NGD (native generic database) ÆÄÀÏÀº NGDBuild ½ÇÇàÀ¸·Î ¹ß»ýµÇ´Â Ãâ·ÂÀÌ´Ù.  NGD ÆÄÀÏÀº ȸ·Î°¡ óÀ½ »ý¼ºµÉ¶§ »ç¿ëµÈ °èÃþ°ú °èÃþÀ» Ǫ´Â ³·Àº ´Ü°èÀÇ ÀÚÀϸµ½º ±âº»¿ä¼Ò¿¡ °üÇÏ¿© Ç¥ÇöµÈ ȸ·ÎÀÇ ³í¸®ÀûÀÎ ±â¼úÀ» Æ÷ÇÔÇÑ´Ù.

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NGD2EDIF
NGD2EDIF´Â ¶ó¿ìÆà µÇ±â ÀüÀ̳ª ÈÄÀÇ ½Ã¹Ä·¹À̼ÇÀ» ÇϱâÀ§ÇÑ ÀÚÀϸµ½º ±âº»ÀûÀÎ ¶óÀ̺귯¸® ÁýÇÕ¿¡ °üÇÏ¿© EDIF 2.1.0ÀÇ ³×Æ®¸®½ºÆ®¸¦ »ý¼ºÇÏ´Â ÇÁ·Î±×·¥ÀÌ´Ù.

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NGD2VER
NGD2VER´Â ȸ·Îµµ¸¦ ½Ã¹Ä·¹À̼ǿëÀÎ ÀÚÀϸµ½º ½Ã¹Ä·¹ÀÌ¼Ç ±âº»Àû¿ä¼Ò¿¡ °üÇÏ¿© ȸ·ÎÀÇ ³×Æ®¸®½ºÆ® ±â¼úÀ» Æ÷ÇÔÇÏ´Â Verilog HDL·Î ¹ø¿ªÇÏ´Â ÇÁ·Î±×·¥ÀÌ´Ù.

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NGD2VHDL
NGD2VHDL´Â ȸ·Îµµ¸¦ ½Ã¹Ä·¹À̼ǿëÀÎ ÀÚÀϸµ½º ½Ã¹Ä·¹ÀÌ¼Ç ±âº»Àû¿ä¼Ò¿¡ °üÇÏ¿© ȸ·ÎÀÇ ³×Æ®¸®½ºÆ® ±â¼úÀ» Æ÷ÇÔÇÏ´Â Vital 3¿¡ µû¸£´Â VHDL·Î ¹ø¿ªÇÏ´Â ÇÁ·Î±×·¥ÀÌ´Ù.

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NGDAnno
NGDAnno programÀº physical NCD file¿¡¼­ logical NGD file¿¡ delay, setup-hold time, pulse width¸¦ ºÐ¹èÇØÁÖ´Â programÀ¸·Î, NGM file·ÎºÎÅÍ Mapping informationÀ», NCD file·ÎºÎÅÍ timing informationÀ» mergeÇÏ¿© NGA file¿¡ ÀúÀåÇÑ´Ù.

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NGDBuild
NGDBuild ÇÁ·Î±×·¥Àº XNF³ª EDIF Çü½ÄÀÇ ³×Æ®¸®½ºÆ® ÆÄÀÏÀ» ÀÐ°í ³í¸®ÀûÀΠȸ·Î¸¦ ±â¼úÇÏ´Â NGD ÆÄÀÏÀ» »ý¼ºÇϴµ¥ ÇÊ¿äÇÑ ¸ðµç ´Ü°è¸¦ ¼öÇàÇÑ´Ù.

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NGM file
NGM (native generic mapping) ÆÄÀÏÀº MAP ½ÇÇàÀ¸·Î ¹ß»ýµÈ Ãâ·ÂÀÌ°í ȸ·Î¿¡ ´ëÇÑ ÇÒ´ç Á¤º¸¸¦ Æ÷ÇÔÇÑ´Ù.  NGM ÆÄÀÏÀº NGDAnno ÇÁ·Î±×·¥ÀÇ ÀÔ·Â ÆÄÀÏÀÌ´Ù.

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number of clock cycles
number of clock cycleÀº snapshot°ú snapshot»çÀÌ¿¡ Á¸ÀçÇÏ´Â clockÀÇ ¼ö¸¦ ³ªÅ¸³»´Âµ¥ synchronous mode debugging°úÁ¤¿¡¼­, º¹¼ö°³ÀÇ snapshotÀ» ÃßÃâÇÒ ¶§, number of snapshotÀÌ °¢°¢ÀÇ snapshotÀ» ÃßÃâÇÏ´Â ±âÁØÁ¡À¸·Î »ç¿ëµÈ´Ù.

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O

one-to-one logic
Xilinx FPGA device¿¡¼­ one-to-one logicÀº design ÀԷ´ܰ迡¼­ÀÇ logic°ú device¿¡ ±¸ÇöµÈ logic»çÀÌÀÇ ÀÏ´ëÀÏ »ó°ü°ü°è¸¦ ÀǹÌÇÑ´Ù.  ÀϷʷΠȸ·Îµµ¿¡¼­ 3°³ÀÇ Inverter¸¦ ÀÔ·ÂÇÏ¿´´Ù¸é programµÈ device»ó¿¡µµ »óÀÀÇÏ´Â 3°³ÀÇ inverter°¡ À§Ä¡ÇÑ´Ù.  ÀÌ·¯ÇÑ »ó°ü°ü°è´Â back-annotationµÈ timing delayÀÇ Á¤È®¼ºÀ» Á¦°íÇϸç, ÀÔ·ÂµÈ design°ú ±¸ÇöµÈ device»óÀÇ logic°ú ÀÏÄ¡µÈ´Ù´Â °ÍÀ» º¸ÀåÇÑ´Ù.

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optimization
OptimizationÀº µðÀÚÀÎ size¸¦ °¨¼Ò ½ÃÅ°°Å³ª speed¸¦ Áõ°¡ ½ÃÅ°´Â °úÁ¤ÀÌ´Ù.

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P

pad
pad¶õ ICÀÇ Silicon°ú Package Frame°£À» ¿¬°áÇϱâ À§ÇÑ bonding pad¸¦ ÀǹÌÇÑ´Ù.  chip»óÀÇ ¸ðµç ½ÅÈ£µéÀº ¹Ýµå½Ã ÀÌpad¸¦ ÅëÇØ ÀԷµǰųª Ãâ·ÂµÇ°Ô µÇ¾îÀÖ´Ù.  pad´Â chipÀÇ package»óÀÇ pin¿¡ ¿¬°áµÇ¾î À־ signalµéÀÌ IC package·Î ÀÔ·Â ¶Ç´Â Ãâ·ÂµÉ ¼ö ÀÖ°Ô µÇ¾îÀÖ´Ù.

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PAR (Place and Route)
PAR´Â ȸ·Î¸¦ ¹èÄ¡ÇÏ°í ¿¬°áÇÏ¿© NCD ÆÄÀÏÀ» Ãâ·ÂÇÏ´Â ÇÁ·Î±×·¥ÀÌ´Ù.  PAR¿¡ ÀÇÇØ »ý¼ºµÈ NCD ÆÄÀÏÀº ´Ù½Ã ¹Ýº¹µÇ´Â¹èÄ¡¿Í ¿¬°áÀ» À§ÇÑ Âü°í ÆÄÀÏ·Î »ç¿ëµÉ ¼ö ÀÖ´Ù.  NCD ÆÄÀÏÀº ¶ÇÇÑ ºñÆ®½ºÆ®¸² ¹ß»ý±âÀÎ BitGen¿¡ ÀÇÇØ »ç¿ëµÇ¾î Áú ¼ö ÀÖ´Ù.

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path delay
°æ·Î Áö¿¬½Ã°£Àº ½ÅÈ£°¡ °æ·Î¸¦ ÅëÇÏ¿© ÀüÇØÁö´Âµ¥ °É¸®´Â ½Ã°£ÀÌ´Ù.

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PCF file
PCF ÆÄÀÏÀº MAP ÇÁ·Î±×·¥ÀÇ Ãâ·Â ÆÄÀÏÀÌ´Ù.  MAP ÇÁ·Î±×·¥¿¡ÀÇÇØ »ý¼ºµÇ´Â ¹°¸®ÀûÀÎ Á¦ÇÑ»Ó ¾Æ´Ï¶ó »ç¿ëÀÚ¿¡ ÀÇÇØ Á¤ÀÇµÈ ¹°¸®ÀûÀÎ Á¦ÇÑÀ» Æ÷ÇÔÇÑ ASCII ÆÄÀÏÀÌ´Ù.  »ç¿ëÀÚ´Â EPIC¾È¿¡¼­ PCF ÆÄÀÏÀ» ÆíÁýÇÒ ¼ö ÀÖ´Ù.

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physical Design Rule Check (DRC)
¹°¸®ÀûÀΠȸ·Î ±ÔÄ¢ °Ë»ç´Â ȸ·Î¿¡¼­ ³í¸®ÀûÀÌ°í ¹°¸®ÀûÀÎ ¿À·ù¸¦ ¹ß°ßÇϱâ À§ÇÑ ÀÏ·ÃÀÇ °Ë»çÀÌ´Ù.  ¹°¸®ÀûÀΠȸ·Î ±ÔÄ¢ °Ë»ç´Â EPIC, BitGen, PAR ±×¸®°í Hardware Debugger·Î ºÎÅÍ Àû¿ëµÈ´Ù.  ±âº»ÀûÀ¸·Î, ¹°¸®ÀûÀΠȸ·Î ±ÔÄ¢ °Ë»ç´Â ÇöÀç ÀÛ¾÷ Àå¼Ò¿¡ ¾²¿©Áø´Ù.

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physical macro
¹°¸®ÀûÀÎ ¸ÅÅ©·Î´Â ƯÁ¤ÇÑ µð¹ÙÀ̽º±ºÀÇ ¿ä¼Ò·Î ºÎÅÍ »ý¼ºµÈ ³í¸®Àû ±â´ÉÀÌ´Ù.  ¹°¸®ÀûÀÎ ¸ÅÅ©·Î´Â È®ÀåÀÚ .nmc ÆÄÀÏ·Î ÀúÀåµÈ´Ù.  ¹°¸®ÀûÀÎ ¸ÅÅ©·Î´Â EPICÀÌ ¸ÅÅ©·Î ¸ðµåÀ϶§ »ý¼ºµÈ´Ù.

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pin
ÇÉÀº ½Éº¼ÀÇ ÇÉÀ̳ª ÆÐÅ°ÁöÀÇ ÇÉ ÀÏ ¼ö ÀÖ´Ù.  ÆÐÅ°ÁöÇÉÀº ICÀÇ ³»ºÎ¿Í ¿ÜºÎ·Î ½ÅÈ£¸¦ ÁÖ°í¹Þ´Â ICÆÐÅ°Áö»óÀÇ ¹°¸®ÀûÀÎ ¿¬°á±âÀÌ´Ù.  ÀνºÅϽº ÇÉÀ¸·Î ¾ð±ÞµÇ´Â ½Éº¼ÇÉÀº ³×Æ®¿¡ ÀνºÅϽºÀÇ ¿¬°áÁ¡ÀÌ´Ù.  pinÀº ChipÀÇ package»óÀÇ pin ¶Ç´Â ȸ·Î»óÀÇ symbolÀÇ pinÀ» °¡¸®Å²´Ù.  Package pinÀº signalµéÀÌ chipÀ¸·Î µé¾î¿À°Å³ª ³ª°¡´Â ⱸ¿ªÇÒÀ» ÇÏ´Â package»óÀÇ pinÀ̸ç, symbol pinÀº ȸ·Î»ó¿¡¼­ net¿Í ÇØ´ç symbolÀÇ ³»ºÎ¿ÍÀÇ ¿¬°á pointÀÌ´Ù.

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pinwires
ÇÉ¿ÍÀ̾î´Â CLB, IOBµîÀÇ ÇÉ¿¡ Á÷Á¢ ¿¬°áµÈ ¿¬°á¼±ÀÌ´Ù.

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place effort
Place effort´Â Flow Engine¿¡¼­ ½ÇÇà½Ã°£°ú placementÈ¿´ÉÀÇ »ó°ü°ü°è¸¦ ÁöÁ¤ÇÏ´Â »ç¿ëÀÚ Á¤ÀÇ parameterÀÌ´Ù.  effort°¡ highÀ̸é È¿´ÉÀº ³ô¾ÆÁöÁö¸¸ ½ÇÇà½Ã°£Àº ±æ¾îÁø´Ù.

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placer
placer´Â ¼³°èÇÑ logicÀ» »ç¿ëÇÏ°íÀÚ ÇÏ´Â ¸ñÇ¥ FPGA chip»óÀÇ Æ¯Á¤À§Ä¡·Î ¹èÄ¡ÇÏ´Â ¿ªÇÒÀ» ¼öÇàÇÑ´Ù.

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placing
PlacingÀº device cell»óÀÇ ¹°¸®Àû À§Ä¡¿¡ µðÀÚÀλóÀÇ logicÀ» ÇÒ´ç, À§Ä¡½ÃÅ°´Â °úÁ¤ÀÌ´Ù.

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primitive
primitive´Â silicon»óÀÇ ±âº»ÀûÀÎ component¿¡ Á÷Á¢ mappingµÇ´Â logic elementÀÌ´Ù.

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probing
ProbingÀº FPGAÀÇ »óŸ¦ °Ë»çÇÏ´Â °úÁ¤ÀÌ´Ù.

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PROG pin
PROGÇÉÀº XCheckerÀÇ pinÀ¸·Î reprogramÆÞ½º¸¦ XC4000, XC5200, Virtex deviceÀÇ PROG pin¿¡ °ø±ÞÇÑ´Ù.

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programming
ProgrammingÀº ¼³°èÇÑ logicÀ» FPGA»ó¿¡ Çü¼ºÇÏ´Â ÀÛ¾÷À» ¼öÇàÇÑ´Ù.

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PROM
PROMÀº programmable read-only memoryÀÇ ¾àÀÚÀÌ´Ù.

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PROM file
PROM fileÀº Çϳª ¶Ç´Â ±× ÀÌ»óÀÇ BIT fileÀ̳ª datastream file·Î ±¸¼ºµÇ´Âµ¥, PROM fileÀÇ ±Ô°Ý¿¡´Â Intel MCS-86, Tektronics TEKHEX, Motorola EXORmacs, HEX µîÀÇ ³× °¡Áö°¡ ÀÖ´Ù.  PROM fileÀº bitstreamÀÇ ±æÀÌ¿¡ ´ëÇÑ Á¤º¸¸¦ Æ÷ÇÔÇÏ´Â header¿Í FPGAÀÇ logicÀ» ±¸¼ºÇϴµ¥ ÇÊ¿äÇÑ ±¸Á¶ (frame) ¿Í control¿¡ °üÇÑ Á¤º¸·Î ±¸¼ºµÈ´Ù.  PROM file·Î´Â Çϳª ¶Ç´Â º¹¼ö °³ÀÇ device¸¦ ÇÁ·Î±×·¥ ÇÒ ¼ö ÀÖ´Ù.

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R

RBT file
RBTÆÄÀÏÀº BIT Çü½ÄÀÇ ¿ø½Ã file·Î ASCII¹öÀüÀÇ BIT ÆÄÀÏÀÌ´Ù.

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RD pin
RDÇÉÀº XCheckerÀÇ readback data pinÀÌ´Ù.

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readback
FPGA device¿¡ downloadµÈ Logic Data¸¦ Computer·Î ÀÐ¾î µéÀÌ´Â °úÁ¤.  Readback¿¡´Â µÎ °¡Áö TypeÀÌ Á¸ÀçÇÑ´Ù.  Ã¹Â°, FPGA¿¡ DownloadµÈ configuration bits¸¦ Àоîµé¿© ´Ù¿î·Îµå°¡ ¹Ù¸£°Ô µÇ¾ú´ÂÁö¸¦ °ËÁõÇϱâ À§ÇÑ Readback.  µÑ°, µ¿À۵ǰí ÀÖ´Â FPGA»óÀÇ ¸Þ¸ð¸® ¿ä¼Ò³ª CLBÀÇ Ãâ·Â, IOBÀÇ Ãâ·Â »óŸ¦ ÀÐ¾î µé¿©¼­ µð¹ÙÀ̽º°¡ ¿øÇÏ´Â ´ë·Î µ¿ÀÛÇÏ°í Àִ°¡¸¦ È®ÀÎÇϱâ À§ÇØ Readback.

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route effort
Flow Engine (Place & Router ToolÀÎ Design ManagerÀÇ Sub-Tool)¿¡¼­ run-time ½Ã°£°ú routingÈ¿À²°úÀÇ °ü°è¸¦ ¼³Á¤ÇÏ´Â User ÆĶó¹ÌÅÍÀÌ´Ù. (High Effort¸¦ ¼³Á¤Çϸé È¿À²Àº ³ô¾ÆÁöÁö¸¸ ½Ã°£Àº ¸¹ÀÌ ¼Ò¿äµÈ´Ù.)

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route-through
»ç¿ëµÇ°Å³ª »ç¿ëµÇÁö¾Ê´Â CLB ¸¦ À§Ä¡¸¦ °æÀ¯ÇÒ ¼ö ÀÖ´Â ¿¬°áÀ» route-through¶ó ºÒ¸°´Ù.  »ç¿ëÀÚ´Â EPIC¿¡¼­ route-through¸¦ ¼öÀÛ¾÷À¸·Î ÇÒ ¼ö ÀÖ´Ù.  Route-through´Â ¹Ý¸é »ç¿ëµÉ ¼ö ¾ø´Â ¶ó¿ìÆà ÀÚ¿øÀ» »ç¿ëÀÚ¿¡°Ô Á¦°øÇÑ´Ù.

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router
µðÀÚÀÎÀÇ net¸¦ »ý¼ºÇϱâ À§ÇØ ¸ðµç ÀûÇÕÇÑ pinµéÀ» ¿¬°áÇÑ´Ù.

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routing
logic netµéÀ» FPGA»ó¿¡ logic cellµéÀ» ¿¬°áÇϱâÀ§ÇØ Á¸ÀçÇÏ´Â ¹°¸®ÀûÀÎ wire·Î ÇÒ´çÇÏ´Â °úÁ¤.  FPGA¿¡¼­ ·ÎÁ÷ ¼¿µé°£À» ¿¬°áÇÏ¿© ³í¶óÀûÀÎ ³×Æ®¸¦ ¹°¸®ÀûÀÎ ¿¬°á¼±¿¡ ºÎºÐÀûÀ¸·Î ÇÒ´çÇϴ ó¸®.

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RPM
Relationally placed macroÀÇ ¾àÀÚ·Î logicÀ» ±¸¼ºÇÏ´Â primitiveµéÀÇ chip»ó¿¡¼­ÀÇ °ø°£ÀûÀÎ À§Ä¡ °ü°è¸¦ Á¤ÀÇÇÏ´Â ¸ÅÅ©·ÎÀÌ´Ù.

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RST pin
ConfigurationµÈ ÈÄ¿¡ target FPGAÀÇ ³»ºÎ Latch³ª Flip-FlopÀ» reset½ÃÅ°±âÀ§ÇØ Low level¸¦ Àΰ¡ÇÒ ¼ö ÀÖ´ÂXcheckerÀÇ pin.

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RT pin
XcheckerÀÇ readback trigger pin.

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S

schematic
User°¡ »ý¼ºÇÏ¿´°Å³ª library·Î Á¦°øµÇ´Â Component¸¦ »ç¿ëÇÏ¿© µðÀÚÀÎÀ» °èÃþÀû ±×¸²À¸·Î Ç¥ÇöÇÑ °ÍÀ» ¸»ÇÑ´Ù (ȸ·Îµµ).

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script
Design Flow¿¡ À־ ÀÏ·ÃÀÇ °úÁ¤µéÀ» ÀÚµ¿ÀûÀ¸·Î ¼öÇàÇϱâ À§ÇÏ¿© ÀÏ·ÃÀÇ ¸í·É¾îµéÀ» file·Î ÀÛ¼ºÇÑ °Í.

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SDF
Standard Delay Format, Timing Simulation¿¡ »ç¿ëµÇ´Â timing Á¤º¸¸¦ ³ªÅ¸³»´Â industry standard file format.

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serial PROM
Single bitÀÇ Data Port¸¦ ÅëÇØ Data¸¦ ReadÇÒ ¼ö ÀÖ´Â PROMÀÌ´Ù.

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setup time
Latch³ª Flip-Flop¿¡¼­ Data°¡ ¾ÈÁ¤µÇ°Ô CatchµÇ´Â °ÍÀ» º¸ÀåÇϱâ À§ÇÏ¿© Clock Event ¹ß»ý¿¡ ¾Õ¼­ ÀÏÁ¤±â°£µ¿¾È ÀÔ·Â Data°¡ ¾ÈÁ¤µÈ »óÅ·ΠÀ¯ÁöµÇ¾î¾ß ÇÏ´Â ½Ã°£.

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snapshot
FPGAÀÇ µ¿ÀÛÁßÀÇ Æ¯Á¤ ¼ø°£¿¡ readbackµÈ Data·Î MemoryÀÇ »óÅ °ª, CLB Ãâ·Â ¶Ç´Â IOBÀÇ ÀÔÃâ·Â °ªÀ» Æ÷ÇÔÇÏ´Â Data.

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states
ƯÁ¤ readback¿¡ ³ªÅ¸³­ ÇØ´ç deviceÀÇ ¸Þ¸ð¸® ¿ä¼Ò (Flip-Flop, Latch, RAM, CLBÃâ·Â, IOB)¿¡ ÀúÀåµÈ °ªÀ» ÀǹÌÇÑ´Ù.  °¢°¢ÀÇ state´Â ƯÁ¤ÇÑ ³í¸®°ª¿¡ ÇØ´çÇÑ´Ù.  Æ¯º°ÇÑ readback ½Ã°£µ¿¾È µð¹ÙÀ̽ºÀÇ »óŸ¦ Ç¥ÇöÇÏ´Â µð¹ÙÀ̽ºÀÇ ±â¾ï¼ÒÀÚ, Áï flip-flops, RAMs, CLB outputs, IOBs¿¡ ÀúÀåµÈ °ª.  °¢°¢ÀÇ »óÅ¿¡¼­´Â ³í¸®ÀûÀÎ °ªÀÇ Æ¯Á¤ÇÑ ÁýÇÕ°ú ÀÏÄ¡ÇÑ´Ù.

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static timing analysis
design networkÀÇ Æ¯Á¤ point·ÎºÎÅÍ point±îÁöÀÇ delay¸¦ ºÐ¼®ÇÏ´Â °Í.

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status bar
ÇöÀç ¼±ÅÃÇÏ¿´°Å³ª ¼öÇàÁßÀÎ ¸í·ÉÀÇ ÁøÇà »óŸ¦ º¸¿©Áִ âÀ¸·Î, ToolÀÇ ÇÏ´Ü¿¡ À§Ä¡ÇÑ ¿µ¿ªÀ» ¸»ÇÑ´Ù.

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synchronous debugging
XChecker cableÀ» »ç¿ëÇÏ¿© Clock¿¡ ´ëÇÑ Àû±ØÀûÀÎ Á¦¾î¸¦ ÇàÇÏ´Â µð¹ö±ë ¸ðµå.

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synthesis
Logic synthesis¸¦ ÂüÁ¶ÇϽÿÀ.

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T

TCK pin
XC9500 µð¹ÙÀ̽ºÀÇ boundary scan port¿¡ clock¸¦ °ø±ÞÇÏ´Â Xchecker pin.  Xchecker cable·Î boundary scan port¸¦ Á¦¾îÇϱâ À§Çؼ­´Â ¹Ýµå½Ã JTAG ¼ÒÇÁÆ®¿þ¾î°¡ »ç¿ëµÇ¾î¾ß ÇÑ´Ù.

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TDI pin
boundary scan chainÀ¸·ÎºÎÅÍ data¸¦ ¹Þ¾ÆµéÀÌ´Â Xchecker pin.  Xchecker cable·Î boundary scan port¸¦ Á¦¾îÇϱâ À§Çؼ­´Â ¹Ýµå½Ã JTAG ¼ÒÇÁÆ®¿þ¾î°¡ »ç¿ëµÇ¾î¾ß ÇÑ´Ù.

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TEKHEX (Tektronix)
Xilinx¿¡ ÀÇÇØ Áö¿øµÇ´Â PROM formatÀ¸·Î ÃÖ´ë ¾îµå·¹½º´Â 65,536ÀÌ´Ù.  ÀÌ formatÀº 8x65,536 = 524,288bit±îÁöÀÇ PROM fileÀ» Áö¿øÇÑ´Ù.

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timing
Timing Process´Â logic cell°ú routingµÈ netµé¿¡ ÀÇÇØ Çü¼ºµÈ delay¸¦ °è»êÇÏ´Â °úÁ¤ÀÌ´Ù.

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Timing constraints
ŸÀÌ¹Ö Á¦¾àµéÀº ¼³°è¿¡ °æ·ÎµéÀÇ ÁÖ¾îÁø ÁýÇÕ¿¡¼­ ÃÖ´ë Çã¿ëÇÒ ¼ö ÀÖ´Â Áö¿¬ÀÇ »ç¿ëÀÚ ½Ã¹æ¼­ÀÌ´Ù.  Å¸ÀÌ¹Ö Á¦¾àµéÀº Schematic ȤÀº »ç¿ëÀÚ Á¦¾à ÆÄÀÏ (UCF)¿¡¼­ ±âÀÔÇÒ ¼ö ÀÖ´Ù.

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TMS pin
TMS ÇÉ.  TMS ÇÉÀº XChecker ÇÉÀÌ´Ù.  ÀÌ Ãâ·ÂÀº ¹Ù¿î´õ¸® ½ºÄµ »óÅ ±â±â ¸ðµå¸¦ ±¸µ¿ÇÑ´Ù.  JTAG ¼ÒÇÁÆ®¿þ¾î´Â XChecker ÄÉÀÌºí¿¡¼­ ¹Ù¿î´õ¸® ½ºÄµ Æ÷Æ®¸¦ ±¸µ¿ÇØ¾ß ÇÑ´Ù.

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Toolbar
µµ±¸¸·´ë´Â À©µµ¿ìÀÇ À§¿¡¼­ ¸Þ´º ¸·´ë ¾Æ·¡¿¡ À§Ä¡ÇÑ´Ù.  ±×°ÍÀº °¡Àå ÀϹÝÀûÀ¸·Î »ç¿ëµÈ ¸í·ÉµéÀÇ ½ÇÇàÀ» À§ÇØ Å¬¸¯ÇÏ¸ç ¹öÆ°ÀÇ ½Ã¸®Á Æ÷ÇÔÇÑ´Ù.  ÀÌ ¹öÆ°µéÀº ¸Þ´º ¸í·Éµé¿¡ ´ëÇÑ ´ë¾ÈÀÌ´Ù.

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Toolbox
µµ±¸»óÀÚ´Â Design Manager ÁÖ À©µµ¿ì¿¡ À§Ä¡ÇÑ´Ù.  ±×°ÍÀº ÀÌ·± ÅøµéÀ» ºÎ¸£±â À§ÇØ ¹öÆ°ÀÇ ½Ã¸®Á Æ÷ÇÔÇÑ´Ù.

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Top-down design
ÇϾç½Ä ¼³°è´Â Ãß»ó °ü³äÀÇ °¡Àå ³ôÀº ¼öÁØ°ú Â÷Â÷ ¼³°è ¹Ø¿¡ ÀÖ´Â ºí·ÏµéÀ» °¡Áö°í ¼³°è¸¦½ÃÀÛÇÑ´Ù.

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TRCE
TRCE´Â ÀÌ¿ë°¡´ÉÇÑ Å¸ÀÌ¹Ö Á¦¾àÁ¶°ÇÀ» »ç¿ëÇÑ È¸·Î»óÀÇ Å¸ÀÌ¹Ö ºÐ¼®À» ÀÚµ¿ÀûÀ¸·Î ¼öÇàÇÒ ÇÁ·Î±×·¥ÀÌ´Ù.  TRCEÀÇ ÀÔ·ÂÀº mapµÈ NCDÆÄÀÏÀÌ°í ¼±ÅÃÀûÀ¸·Ð PCF ÆÄÀÏÀÌ´Ù.  TRCEÀÇ Ãâ·ÂÀº »ç¿ëÀÚÀÇ È¸·Î°¡ ŸÀÌ¹Ö Á¶°ÇµéÀÌ ¾ó¸¶³ª Àß ¸Â¾Ò´ÂÁö Ç¥½ÃÇÏ´Â ASCIIÇü½ÄÀÇ Å¸ÀÌ¹Ö º¸°í¼­ÀÌ´Ù.

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TRIG pin
TRIG ÇÉ.  TRIG ÇÉÀº XChecker ¿ÜºÎÀÇ Æ®¸®°Å ÇÉÀÌ´Ù.  ±×°ÍÀº µð¹ÙÀ̽º¿¡ Á¸ÀçÇÏ´Â µð¹ö±×ÀÇ ReadbackÀ» ½ÃÀÛÇϱâ À§ÇÑ Hardware Debugger ¿øÀÎÀÌ´Ù.

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Trigger
Æ®¸®°Å´Â ¿ÜºÎ¿¡¼­ ¿À´Â ½ÅÈ£ÀÌ´Ù.  ±×°ÍÀº SnapshotÀ» Àбâ À§ÇØ Hardware Debugger·Î ÀüÇÑ´Ù.

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TTY
TTY´Â ¿ø¹®ÀÇ ¸í·É¾î ÁÙ ÀÎÅÍÆäÀ̽ºÀÌ´Ù.

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TWR file
TWR ÆÄÀÏÀº TRCE ÇÁ·Î±×·¥ÀÇ Ãâ·ÂÀÌ´Ù.  TWR ÆÄÀÏÀº ȸ·Î°¡ óÀ½ »ý¼ºµÉ¶§ »ç¿ëµÈ °èÃþ¿¡ °üÇÑ°Í°ú °èÃþÀ» Ǭ Á» ´õ ³·Àº ´Ü°èÀÇ xilinx±âº»¿ä¼Ò¿¡ °üÇÑ, µÑ ¸ðµÎ°¡ Ç¥ÇöµÈ ȸ·ÎÀÇ ³í¸®ÀûÀÎ ±â¼úÀ» Æ÷ÇÔÇÑ´Ù.

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U

UCF file
UCF´Â »ç¿ëÀÚ°¡ ÁöÁ¤ÇÑ ³í¸®ÀûÀÎ Á¦¾àÁ¶°ÇÀ» Æ÷ÇÔÇÑ´Ù.

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Universal Interconnect Matrix (UIM)
UIMÀº CPLD µð¹ÙÀ̽ºµéÀ» À§ÇÑ ¹è¼± ¸ÅÆ®¸¯½ºÀÌ´Ù.  ÀÌ°ÍÀº ÃæºÐÈ÷ ¸ðµç Ãâ·ÂÀº ¸ðµç ÀԷ¿¡ ¹è¼±ÇÏ¸ç ¸ðµç ¼³°èÀÇ 100% Routability º¸ÁõÀ» ÆÄÇ÷¹ÀÌÆ® ±³È¯ ¸ÅÆ®¸¯½º´Â Çã¿ëÇÑ´Ù.

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V

VCC pin
VCC ÇÉ.  Àü¿ø (5 Volts).

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Verification
°ËÁõÀº µð¹ÙÀ̽ºÀÇ ±¸¼º µ¥ÀÌÅ͸¦ ¿ªÀ¸·Î Àб⠱׸®°í ±×°ÍÀ» º»·¡ÀÇ ¼³°è¿Í ºñ±³ÇÏ¿© ó¸®ÇÑ´Ù.

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Verilog
Verilog´Â ÀϹÝÀûÀ¸·Î »ç¿ëµÈ Çϵå¿þ¾î ±â¼ú ¾ð¾îÀÌ´Ù.  ±×°ÍÀº µðÁöÅÐ ½Ã½ºÅÛ ¸ðÇüÀ» À§ÇØ¾Ë°í¸®ÁòÀÇ ¼öÁغÎÅÍ °ÔÀÌÆ® ¼öÁرîÁö Ãß»ó °ü³ä ¹üÀ§ÀÇ ¸¹Àº ¼öÁØ¿¡¼­ »ç¿ëÇÏ¿´´Ù.

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VHDL
VHDLÀº VHSIC Hardware Description Language¸¦ À§ÇÑ ¸Ó¸´ ±ÛÀÚ¸»ÀÌ´Ù.  (VHSICÀº Very High-Speed Integrated CircuitsÀÇ ¸Ó¸´ ±ÛÀÚ¸»ÀÌ´Ù.)  ÀÌ°ÍÀº Çϵå¿þ¾î ±â¼ú ¾ð¾îÀÌ¸ç µðÁöÅÐ ½Ã½ºÅÛ ¸ðÇüÀ» À§ÇØ ¾Ë°í¸®ÁòÀÇ ¼öÁغÎÅÍ °ÔÀÌÆ® ¼öÁرîÁö Ãß»ó °ü³ä ¹üÀ§ÀÇ ¸¹Àº ¼öÁØ¿¡¼­ »ç¿ëÇÏ¿´´Ù.

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W

Waveform
Hardware Debugger¿¡¼­ WaveformÀº Çϳª ȤÀº ´õ ¸¹Àº Snapshot ±×·¡ÇÁÀÇ Ç¥ÇöÀÌ´Ù.  °¢ SnaopshotÀº µð¹ÙÀ̽º ¸Þ¸ð¸® ¼ÒÀÚÀÇ °³°³ÀÇ »óŸ¦ Ç¥ÇöÇÑ´Ù.

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WIR file
WIR ÆÄÀÏ.  WIRÆÄÀÏÀº Áß°£ÀÇ ¼³°è ÆÄÀÏÀÌ´Ù.  ±×°ÍÀº Viewlogic µðÀÚÀÎ ÅøÀÌ ¸¸µç´Ù.

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wire
wire´Â ³×Æ®À̰ųª ½ÅÈ£ÀÌ´Ù.

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Workspace
PROM File Formatter¿¡¼­ Workspace´Â ÇÁ·¹ÀÓ°ú ºó µ¥ÀÌÅÍ ½ºÆ®¸²ÀÌ´Ù.  µ¥ÀÌÅÍ ½ºÆ®¸²¿¡ ÆÄÀÏÀ» Ãß°¡ÇÏ¿´À»¶§ ¼öÆò È­»ìÀº ÆÄÀÏÀÇ ¿¬°áÀ» °¡¸£Å²´Ù.

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