Starting the Timing Analyzer

The Timing Analyzer runs on PCs and workstations. On the PC, the graphical user interface is based on Microsoft Windows. On the workstation, the interface is based on OSF Motif.

You can start the Timing Analyzer from the Windows Program Manager, the Xilinx Design Manager, or the command line.

From the Design Manager

To start the Timing Analyzer from the Design Manager window (PC or workstation), click on the Timing Analyzer icon, shown in the following figure. Or select the Tools Timing Analyzer menu command.

Stand-Alone Tool

If you installed the Timing Analyzer as a stand-alone tool on a PC, click on the Timing Analyzer icon (shown in the previous figure) on the Windows desktop or select timingan.exe from the Windows 95 or Windows NT Start button.

From the Command Line

To start the Timing Analyzer from a UNIX command line, type the following command.

timingan

These are three variations for starting the Timing Analyzer from the command line.

• To run the tool as a background process, type the following.
  
  timingan &
  
  
• To start the Timing Analyzer and open an existing FPGA or CPLD design, type the following.
  
  timingan {design_name.ncd|design_name.vm6} &
  
  For FPGA designs, if a physical constraints file (PCF) exists in the same directory as the design and has the same name, except for the extension, that design_name.pcf file is automatically opened.
  
  
• To start the tool, open an existing FPGA design and the corresponding physical constraints file, type the following. Physical constraints files only apply to FPGAs.
  
  timingan design_name.ncd -pcf pcf_file_name.pcf &