Basic Timing Analysis Procedure

The typical procedure for using the Timing Analyzer is as follows.

Open the Timing Analyzer and load a design.

For FPGAs, if a physical constraints file (PCF) with the same name as the design exists in the directory, the Timing Analyzer also loads that file, by default. (The PCF file is generated when a design is mapped.)
If you are unfamiliar with the Timing Analyzer, explore its features. You can use the online help facility to help you with this process. To run the online help, select Help Help Topics.
You can optionally generate a report to obtain a basic overview of the design's timing before you begin to analyze it in detail. The Advanced Design Analysis report provides that information. Choose the Advanced Design command from the Analyze menu to generate and display an Advanced Design Analysis report.
Select commands from the Path Filters menu to determine which types of paths to analyze and report. You can filter out paths you are not interested in.
Select commands from the Options menu to change the speed grade for analysis or to specify report options.
Select commands from the Analyze menu to specify the kinds of reports you want to generate.
Select commands from the Edit menu to search or edit reports.
Select commands from the File menu to save or print reports.
Optionally, you can create macros comprising the commands just issued.