AnalyzeAdvancedDesign

The AnalyzeAdvancedDesign command generates an Advanced Design Analysis report. This report, which provides a set of summary statistics for the paths from the timing requirements specified for analysis.

For FPGAs, this report displays the results of analyzing the constraints specified in the constraints file. If no constraints are specified, this report displays the maximum clock frequencies for all clocks in the design and the worst-case timing for all clock paths. For CPLDs, the Design Performance report lists all external Pad to Pad (tPD), Clock Pad to Output Pad (tCO), Setup to Clock at the Pad (tSU) and delays, and internal Clock to Setup (tCYC) delays.

This command is equivalent to the Analyze Advanced Design menu command.

NOTE

The AnalyzeAdvancedDesign command was previously named AnalyzeDesignPerformance and had the abbreviation adp. You can still use AnalyzeDesignPerformance and adp for this release of the software, but they will be phased out in a subsequent release.

Syntax

The syntax of the AnalyzeDesignPerformance command is the following.

AnalyzeAdvancedDesign [save file_name.twr]

• Save indicates that you can optionally save the Advanced Design Analysis report in a file. If this option is not specified, the report appears in a window.
  
  
• File_name is the name of the file in which the Design Performance report is saved. TWR is the extension for report files.
  
  

Abbreviation

Abbreviate the AnalyzeAdvancedDesign command syntax as follows.

aap [s file_name.twr]

Example

The following is an example of the AnalyzeAdvancedDesign command.

analyzeadvanceddesign save shelby.twr