The Speed command sets the speed grade during analysis. Changing the speed grade helps you determine if you need to target a faster device to meet your timing requirements, or if using a slower speed grade still meets timing constraints. The speed grade is set in the design file, NCD for FPGAs or VM6 for CPLDs. Using this command does not affect the speed grade set in the design file.
This command is equivalent to the Options 
Speed Grade menu command.
The syntax of the Speed command is the following.
speed speed_grade
Speed_grade can be any of the speed grades available for the architecture used. You can obtain this information from the Design Manager or the Timing Analyzer's graphical interface.
You can abbreviate the Speed command syntax as follows.
sp speed_grade
Following is an example of the Speed command.
speed -3
