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DefineEndPoints

The DefineEndPoints command selects the starting and ending points of the paths that you want to analyze.

This command is equivalent to the Path Filters Custom Filters Select Sources and the Path Filters Custom Filters Select Destinations menu commands.

FPGA starting and ending points are: flip-flops, pads, nets, pins, CLBs, RAMs, Latches, or clocks. CPLD starting and ending points are: flip-flops, pads, nets, macrocells, or clocks.

Syntax

The syntax of the DefineEndPoints command is the following.

DefineEndPoints {FromAll|ToAll}
DefineEndPoints {FromPad|ToPad}
pad_name
DefineEndPoints {FromCLB|ToCLB} CLB_name
DefineEndPoints {FromNet|ToNet} net_name
DefineEndPoints {FromPin|ToPin} pin_name
DefineEndPoints {FromFF|ToFF} flip-flop_name
DefineEndPoints {FromEitherEdge|ToEitherEdge} clock_name
DefineEndPoints {FromRising|ToRising} clock_name
DefineEndPoints {FromMacrocell|ToMacrocell} macrocell_name
DefineEndPoints {FromFalling|ToFalling} clock_name

The defaults are FromAll and ToAll.

In the DefineEndPoints command syntax, you can enter * for pad_name, CLB_name, net_name, pin_name, flop_name, flip-flop_name, clock_name, or macrocell_name to specify all the elements of that type.

Abbreviation

Abbreviate the DefineEndPoints command syntax as follows.

dep {fall|tall}
dep {fpad|tpad}
pad_name
dep {fclb|tclb} CLB_name
dep {fnet|tnet} net_name
dep {fpin|tpin} pin_name
dep {fff|tff} flip-flop_name
dep {fee|tee} clock_name
dep {fris|tris} clock_name
dep {fmc|tmc} macrocell_name
dep {ffal|tfal} clock_name

Example

Following are examples of the DefineEndPoints command.

defineendpoints fromff CNT3Q0 CNT3Q1

defineendpoints topad P80 P68

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