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CLB Count

Configurable Logic Blocks (CLBs) implement most of the logic in an FPGA. The following CLB Count table lists FPGA design elements in alphanumeric order with the number of CLBs needed for their implementation in each applicable library. Refer to the “Applicable Architectures” section of the “Xilinx Unified Libraries” chapter for information on the specific device architectures supported in each library.

Each XC5200 CLB contains four independent Logic Cells™ (LCs). In the following table, the numbers in the XC5200 column are the LC4 count.

Each Virtex CLB contains two slices. In the following table, the numbers in the Virtex column are the combined count for the two slices.

NOTE

This information is for reference only. The actual count could vary, depending upon the switch settings of the implementation tools; for example, the effort level in PAR (Place and Route).

Name
XC3000
XC4000E
XC4000X
XC5200*
Spartan
SpartanXL
Virtex**
ACC4
9
7
7
15
7
7
5
ACC8
17
11
11
27
11
11
9
ACC16
33
19
19
51
19
19
17
ACLK
1
-
-
-
-
-
-
ADD4
5
4
4
10
4
4
3
ADD8
9
6
6
18
6
6
5
ADD16
17
10
10
34
10
10
9
ADSU4
5
4
4
10
4
4
3
ADSU8
9
6
6
18
6
6
5
ADSU16
17
10
10
34
10
10
9
AND2
1
-
-
1
-
-
1
AND3
1
-
-
1
-
-
1
AND4
1
-
-
1
-
-
1
AND5
1
1
1
2
1
1
1
AND6
2
1
1
2
1
1
1
AND7
2
1
1
3
1
1
1
AND8
2
1
1
3
1
1
2
AND9
2
1
1
4
1
1
2
AND12
-
-
-
4
-
-
2
AND16
-
-
-
5
-
-
2
BRLSHFT4
4
4
4
4
4
4
8
BRLSHFT8
12
12
12
12
12
12
12
BSCAN
-
-
-
3
-
-
-
BUFE
1
-
-
-
-
-
-
BUFE4
1
-
-
-
-
-
-
BUFE8
1
-
-
-
-
-
-
BUFE16
1
-
-
-
-
-
-
BUFG
1
-
-
1
-
-
-
BUFGP
-
-
-
1
-
-
-
BUFGS
-
-
-
1
-
-
-
CB2CE
3
2
2
4
2
2
2
CB2CLE
4
3
3
5
3
3
3
CB2CLED
4
3
3
6
3
3
3
CB2RE
3
2
2
4
2
2
2
CB4CE
4
3
3
6
3
3
3
CB4CLE
7
5
5
9
5
5
5
CB4CLED
8
7
7
10
7
7
6
CB4RE
4
4
4
8
4
4
3
CB8CE
8
6
6
13
6
6
6
CB8CLE
13
10
10
18
10
10
9
CB8CLED
14
12
13
22
12
13
12
CB8RE
9
8
8
17
8
8
6
CB16CE
16
12
12
27
12
12
13
CB16CLE
26
18
18
36
18
18
18
CB16CLED
28
25
25
46
25
25
24
CB16RE
18
18
18
35
18
18
13
CC8CE
-
5
5
18
5
5
8
CC8CLE
-
6
6
19
6
6
9
CC8CLED
-
11
11
19
11
11
9
CC8RE
-
5
5
18
5
5
9
CC16CE
-
9
9
34
9
9
16
CC16CLE
-
10
10
35
10
10
17
CC16CLED
-
19
19
35
19
19
17
CC16RE
-
9
9
34
9
9
17
CD4CE
4
3
3
6
3
3
3
CD4CLE
7
5
5
10
5
5
5
CD4RE
5
6
5
9
6
5
3
CD4RLE
10
9
9
17
9
9
7
CJ4CE
2
2
2
4
2
2
2
CJ4RE
2
4
4
4
4
4
2
CJ5CE
3
3
3
5
3
3
3
CJ5RE
3
5
5
5
5
5
3
CJ8CE
4
4
4
8
4
4
4
CJ8RE
4
8
8
8
8
8
4
COMP2
1
1
1
1
1
1
1
COMP4
4
1
1
3
1
1
2
COMP8
9
4
4
5
4
4
3
COMP16
17
9
9
11
9
9
6
COMPM2
3
1
1
5
1
1
1
COMPM4
8
2
2
13
2
2
5
COMPM8
19
8
8
27
8
8
11
COMPM16
39
21
21
64
21
21
24
COMPMC8
-
7
7
18
7
7
8
COMPMC16
-
11
11
34
11
11
16
CR8CE
8
8
8
8
8
8
8
CR16CE
16
16
16
16
16
16
16
CY_INIT
-
-
-
1
-
-
-
CY_MUX
-
-
-
2
-
-
-
D2_4E
2
2
2
4
2
2
2
D3_8E
4
4
4
8
4
4
4
D4_16E
16
16
16
32
16
16
16
DEC_CC4
-
-
-
2
-
-
1
DEC_CC8
-
-
-
3
-
-
1
DEC_CC16
-
-
-
5
-
-
2
DECODE4
-
-
-
2
-
-
1
DECODE8
-
-
-
3
-
-
2
DECODE16
-
-
-
5
-
-
2
DECODE32
-
-
-
9
-
-
4
DECODE64
-
-
-
18
-
-
8
F5_MUX
-
-
-
1
-
-
-
F5MAP
-
-
-
1
-
-
-
FD
1
-
-
1
-
-
-
FD_1
1
-
-
1
-
-
-
FD4CE
4
2
2
4
2
2
2
FD4RE
2
4
4
4
4
4
2
FD8CE
4
4
4
8
4
4
4
FD8RE
4
8
8
8
8
8
4
FD16CE
8
8
8
16
8
8
8
FD16RE
8
16
16
16
16
16
8
FDC
1
1
1
1
1
1
-
FDC_1
1
1
1
1
1
1
-
FDCE
1
1
1
1
1
1
-
FDCE_1
1
1
1
1
1
1
-
FDP
-
1
1
1
1
1
-
FDP_1
-
1
1
1
1
1
-
FDPE
-
-
-
1
-
-
-
FDPE_1
-
1
1
1
1
1
-
FDR
1
1
1
1
1
1
-
FDRE
1
1
1
1
1
1
-
FDRS
1
1
1
1
1
1
-
FDRSE
1
2
2
3
2
2
-
FDS
1
1
1
1
1
1
-
FDSE
1
1
1
1
1
1
-
FDSR
1
1
1
1
1
1
-
FDSRE
1
2
2
3
2
2
-
FJKC
1
1
1
1
1
1
1
FJKCE
1
1
1
1
1
1
1
FJKP
-
1
1
1
1
1
1
FJKPE
-
1
1
1
1
1
1
FJKRSE
2
2
2
3
2
2
1
FJKSRE
2
2
2
3
2
2
1
FTC
1
1
1
1
1
1
1
FTCE
1
1
1
1
1
1
1
FTCLE
1
1
1
2
1
1
1
FTCLEX
-
-
-
-
-
-
1
FTP
-
1
1
1
1
1
1
FTPE
-
1
1
1
1
1
1
FTPLE
-
1
1
2
1
1
1
FTRSE
1
2
2
3
2
2
1
FTRSLE
3
2
2
4
2
2
2
FTSRE
1
2
2
3
2
2
1
FTSRLE
3
2
2
4
2
2
2
GCLK
1
-
-
-
-
-
-
IFD
-
-
-
1
-
-
-
IFD_1
-
-
-
1
-
-
-
IFD4
-
-
-
4
-
-
-
IFD8
-
-
-
8
-
-
-
IFD16
-
-
-
16
-
-
-
ILD
-
-
-
1
-
-
1
ILD_1
-
-
-
1
-
-
1
ILD4
-
-
-
4
-
-
2
ILD8
-
-
-
8
-
-
4
ILD16
-
-
-
16
-
-
8
IOPAD
-
-
-
1
-
-
-
LD
-
-
1
1
-
1
-
LD4
-
-
4
-
-
4
2
LD8
-
-
8
-
-
8
4
LD16
-
-
16
-
-
16
8
LD4CE
-
-
4
4
-
4
2
LD8CE
-
-
8
8
-
8
4
LD16CE
-
-
16
16
-
16
8
LD_1
-
-
1
1
-
1
-
LDC
-
-
1
1
-
1
-
LDC_1
-
-
1
1
-
1
-
LDCE
-
-
1
1
-
1
-
LDCE_1
-
-
-
1
-
-
-
LDPE
-
-
1
-
-
1
-
LDPE_1
-
-
1
-
-
1
-
M2_1
1
1
1
1
1
1
1
M2_1B1
1
1
1
1
1
1
1
M2_1B2
1
1
1
1
1
1
1
M2_1E
1
1
1
1
1
1
1
M4_1E
3
1
1
1
1
1
1
M8_1E
6
3
3
7
3
3
2
M16_1E
11
7
7
14
7
7
5
NAND2
1
-
-
1
-
-
1
NAND3
1
-
-
1
-
-
1
NAND4
1
-
-
1
-
-
1
NAND5
1
1
1
2
1
1
1
NAND6
2
1
1
2
1
1
1
NAND7
2
1
1
3
1
1
1
NAND8
2
1
1
3
1
1
2
NAND9
2
1
1
4
1
1
2
NAND12
-
-
-
4
-
-
2
NAND16
-
-
-
5
-
-
2
NOR2
1
-
-
1
-
-
1
NOR3
1
-
-
1
-
-
1
NOR4
1
-
-
1
-
-
1
NOR5
1
1
1
2
1
1
1
NOR6
2
1
1
2
1
1
1
NOR7
2
1
1
3
1
1
1
NOR8
2
1
1
3
1
1
2
NOR9
2
1
1
4
1
1
2
NOR12
-
-
-
4
-
-
2
NOR16
-
-
-
5
-
-
2
OFD
-
-
-
1
-
-
-
OFD_1
-
-
-
1
-
-
-
OFD4
-
-
-
4
-
-
-
OFD8
-
-
-
8
-
-
-
OFD16
-
-
-
16
-
-
-
OFDE
-
-
-
1
-
-
-
OFDE_1
-
-
-
1
-
-
-
OFDE4
-
-
-
4
-
-
-
OFDE8
-
-
-
8
-
-
-
OFDE16
-
-
-
16
-
-
-
OFDT
-
-
-
1
-
-
-
OFDT_1
-
-
-
1
-
-
-
OFDT4
-
-
-
4
-
-
-
OFDT8
-
-
-
8
-
-
-
OFDT16
-
-
-
16
-
-
-
OR2
1
-
-
1
-
-
1
OR3
1
-
-
1
-
-
1
OR4
1
-
-
1
-
-
1
OR5
1
1
1
2
1
1
1
OR6
2
1
1
2
1
1
1
OR7
2
1
1
3
1
1
1
OR8
2
1
1
3
1
1
2
OR9
2
1
1
3
1
1
2
OR12
-
-
-
4
-
-
2
OR16
-
-
-
5
-
-
2
RAM16X2
-
1
1
-
1
1
-
RAM16X2D
-
2
2
-
2
2
2
RAM16X2S
-
1
1
-
1
1
2
RAM16X4
-
2
2
-
2
2
-
RAM16X4D
-
4
4
-
4
4
4
RAM16X4S
-
2
2
-
2
2
4
RAM16X8
-
4
4
-
4
4
-
RAM16X8D
-
8
8
-
8
8
8
RAM16X8S
-
4
4
-
4
4
8
RAM32X2
-
2
2
-
2
2
-
RAM32X2S
-
2
-
-
2
-
2
RAM32X4
-
4
4
-
4
4
4
RAM32X4S
-
4
4
-
4
4
8
RAM32X8
-
8
8
-
8
8
-
RAM32X8S
-
8
8
-
8
8
-
SOP3
1
1
1
1
1
1
1
SOP4
1
1
1
1
1
1
1
SR4CE
2
2
2
4
2
2
2
SR4CLE
4
3
3
5
3
3
3
SR4CLED
5
5
5
10
5
5
5
SR4RE
2
4
4
4
4
4
2
SR4RLE
6
5
5
9
5
5
3
SR4RLED
7
8
8
14
8
8
5
SR8CE
4
4
4
8
4
4
4
SR8CLE
5
5
5
9
5
5
5
SR8CLED
9
9
9
18
9
9
9
SR8RE
4
8
8
8
8
8
4
SR8RLE
12
9
9
17
9
9
5
SR8RLED
13
9
9
26
9
9
9
SR16CE
8
8
8
16
8
8
8
SR16CLE
9
9
9
17
9
9
9
SR16CLED
17
17
17
34
17
17
17
SR16RE
8
16
16
16
16
16
8
SR16RLE
24
20
20
33
20
20
9
SR16RLED
25
19
19
50
19
19
17
UPAD
-
-
-
1
-
-
-
XNOR2
1
-
-
1
-
-
1
XNOR3
1
-
-
1
-
-
1
XNOR4
1
-
-
1
-
-
1
XNOR5
1
1
1
2
1
1
1
XNOR6
2
1
1
2
1
1
1
XNOR7
2
1
1
3
1
1
1
XNOR8
2
1
1
3
1
1
2
XNOR9
2
1
1
3
1
1
2
XOR2
1
-
-
1
-
-
1
XOR3
1
-
-
1
-
-
1
XOR4
1
-
-
1
-
-
1
XOR5
1
1
1
2
1
1
1
XOR6
2
1
1
2
1
1
1
XOR7
2
1
1
3
1
1
1
XOR8
2
1
1
3
1
1
2
XOR9
2
1
1
3
1
1
2
X74_42
5
5
5
10
5
5
-
X74_L85
14
9
9
20
9
9
-
X74_138
5
5
5
9
5
5
-
X74_139
2
2
2
4
2
2
-
X74_147
8
6
6
12
6
6
-
X74_148
10
6
6
14
6
6
-
X74_150
11
6
6
13
6
6
-
X74_151
6
3
3
7
3
3
-
X74_152
5
3
3
6
3
3
-
X74_153
6
3
3
6
3
3
-
X74_154
17
16
16
33
16
16
-
X74_157
4
2
2
4
2
2
-
X74_158
4
2
2
4
2
2
-
X74_160
8
6
6
11
6
6
-
X74_161
9
5
5
9
5
5
-
X74_162
8
6
6
13
6
6
-
X74_163
10
9
9
17
9
9
-
X74_164
5
4
4
8
4
4
-
X74_165S
8
5
5
9
5
5
-
X74_168
9
7
7
11
7
7
-
X74_174
7
4
4
6
4
4
-
X74_194
7
5
5
12
5
5
-
X74_195
5
3
3
5
3
3
-
X74_273
9
5
5
8
5
5
-
X74_280
3
2
2
5
2
2
-
X74_283
4
6
6
8
6
6
-
X74_298
4
2
2
4
2
2
-
X74_352
6
3
3
6
3
3
-
X74_377
9
4
4
8
4
4
-
X74_390
3
3
3
4
3
3
-
X74_518
9
4
4
6
4
4
-
X74_521
9
4
4
6
4
4
-
*LC4 count
**Combined count for the two Virtex slices
- = zero (0) or the component is not applicable for that architecture

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