| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|
| N/A | Macro | Macro | Macro | Macro | Macro | Macro | Primitive |
FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the Low-to-High clock (C) transition.
For FPGAs, the flip-flop is asynchronously preset, output High, when global reset (GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The active level of the GR/GSR defaults to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.
For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
| Inputs | Outputs | ||
|---|---|---|---|
| PRE | C | D | Q |
| 1 | X | X | 1 |
| 0 |  | 1 | 1 |
| 0 | | 0 | 0 |
Figure 5.15 FDP Implementation XC4000, XC5200, Spartans |  |
Figure 5.16 FDP Implementation XC9000 | |
