FDRSE

D Flip-Flop with Synchronous Reset and Set and Clock Enable

FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock transition. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High clock transition.

The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs					Outputs
R	S	CE	D	C	Q
1	X	X	X		0
0	1	X	X		1
0	0	0	X	X	No Chg
0	0	1	1		1
0	0	1	0		0

Figure 5.25 FDRSE Implementation XC3000, XC4000, XC5200, Spartans

Figure 5.26 FDRSE Implementation XC9000