| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|
| N/A | Macro | Macro | Macro | Macro | Macro | Macro | Macro |
FJKP is a single J-K-type flip-flop with J, K, and asynchronous preset (PRE) inputs and data output (Q). The asynchronous preset (PRE) input, when High, overrides all other inputs and sets the Q output High. When PRE is Low, the Q output responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock transition.
For FPGAs, the flip-flop is asynchronously preset, output High, when global reset (GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The GR/GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.
For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
| Inputs | Outputs | |||
|---|---|---|---|---|
| PRE | J | K | C | Q |
| 1 | X | X | X | 1 |
| 0 | 0 | 0 | X | No Chg |
| 0 | 0 | 1 |  | 0 |
| 0 | 1 | 0 | | 1 |
| 0 | 1 | 1 | | Toggle |
Figure 5.40 FJKP Implementation XC4000, XC5200, Spartans, Virtex |  |
Figure 5.41 FJKP Implementation XC9000 | |
