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Setting Global PRLD (CPLD Designs)

Before you simulate a CPLD design, you must force the global reset, or “PreLoad” (PRLD) signal. Forcing the global preload signal emulates the power-on initialization of the CPLD. If you do not force global preload, the flip-flops and latches have undefined initial states. The PRLD signal is active High. Force it High, then Low to properly initialize the flip-flops in your design at the beginning of a simulation.

If you want to select the PRLD pulse width so that it reflects the actual amount of time it takes for the chip to go through the reset process during power on (Twmr for XC9500 devices), refer to The Programmable Logic Data Book for the appropriate device.

Unified Library Functional Simulation

To simulate PRLD in Verilog-XL using the M1 Unified Library simulation models, define a reg called “PRLD” and set a Verilog macro called “PRLD_SIGNAL to “test.PRLD” as follows.

   module test;
   reg PRLD;
   `define PRLD_SIGNAL test.PRLD;
    
   Toggle this newly defined signal in an initial block:
    
   initial
     begin
        PRLD = 1;     // reset the device
        #100 PRLD = 0;

Alternatively, you can reference the PRLD_SIGNAL macro in your initial block.

   initial
     begin
        `PRLD_SIGNAL = 1;     // reset the device
        #100 `PRLD_SIGNAL = 0;

Post-NGDBuild and Post-Implementation Timing Simulation

To simulate the global PRLD signal in a Verilog post-NGDBuild or post-implementation timing simulation, you can re-use the same test fixture as the one you created for Unified Library functional simulation.

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