Controlling FPGA/CPLD Layout from the Schematic

This section discusses FPGA/CPLD schematic layout.

Assigning Pin Locations

Let the automatic placement and routing program, PAR, define the pinout. Pre-assigning locations to the I/Os can sometimes degrade the performance of the place and route tools. However, at some point you must usually lock the pinout of a design so that it can integrate into a board design. Define the initial pinout by running the place and route tools without pin assignments, then locking down the I/O placement so that it reflects the locations chosen by the tools. As a general rule, place inputs on the left side of the die and outputs on the right. Assign I/O in the tutorial schematics to pin locations so that the Calc design can function in the Xilinx demonstration boards. Because of the simplicity of the design, these pin assignments do not adversely affect the ability of PAR to place and route the design completely.

Specify pin locations by attaching a LOC property to the net attached to the pad. Do not attach LOC properties directly to I/O pads.

Add the LOC property to the OBUF associated with the 7-Segment Display F signal on the Calc schematic as follows.

1. Display the Calc schematic (“edit calc”).
   
   
2. Enter into the Attribute mode.
   
   
3. Select the OBUF to the right of the pad attached to net F. Refer to the following figure. The Attribute Form appears, as shown in the next figure.
   
   
4. Select Add in the Attribute form. In the resulting blank Name field, type “LOC.” In the Value field, type P50.
   
   
   
   

   Figure 9.28 Attribute Form for Adding a LOC

5. Click on Done to execute the command.
   
   
6. Use the Move command to move the “P50” text to a position closer to the OBUF.
   
   

For simplicity, the other pin locations for the Calc design reside in a data file known as a constraint file (described in a later section). You can leave the other location values undefined. Valid pin locations vary depending on the package. A “P” followed by the pin number, such as P17 designates PLCC, HQFP, and other “numeric-only” package pins. PGA and other grid-array package pins use alphanumerics such as A12. The Programmable Logic Data Book lists the pinouts of each FPGA and CPLD for each package that Xilinx supplies.

Figure 9.29 Assigning a Location to an Output Net

Designating FAST Pads

You can modify output slew rate by assigning a FAST attribute to the output buffer, as shown in the “Designating a FAST Pad” figure. The default slew rate is SLOW for FPGAs, FAST for CPLDs. “Fast” pads have different timing specifications and draw more current than “slow” (slew-rate-limited) pads. See The Programmable Logic Data Book for timing specifications for the various slew rate modes.

Add a FAST attribute to the LED output display drivers attached to the STACKLED (3:0) bus as follows.

1. Press F2 to display the entire Calc schematic.
   
   
2. Enter the Attribute mode.
   
   
3. Click the left mouse button on the OBUF4 symbol attached to the STACKLED (3:0) bus.
   
   
4. In the Attribute Form, click on the Add button, and enter “FAST” in the resulting Name field and “TRUE” in the Value field. Click on the button under Display (to the left of the “TRUE” test you just entered) until it displays “Name.”
   
   
5. Press Done to execute the command.
   
   
6. Move the text to be near the OBUF4 symbol, as shown in the following figure. Because the property attaches to the OBUF4 symbol, it affects all four of the LED outputs.
   
   

Figure 9.30 Designating a FAST Pad

Using the I/O Flip-Flops

Xilinx XC3000A and XC4000E devices have two flip-flops in each Input Output Block (IOB), an input flip-flop and an output flip-flop. You can also configure input flip-flops as latches and output flip-flops as 3-state. You access these elements using the library components IFD, ILD, OFD, and OFDT, as well as other higher-level macros that contain these components. For more information on these library elements, consult the Xilinx Libraries Guide.

The design uses IOB flip-flops whenever possible to free up internal CLB resources. In the Calc design, IOB flip-flops register the switch inputs. As shown in the “SWITCH7 Schematic Using Input Flip-Flops” figure, the SWITCH7 macro attached to the input bus SW<6:0> in the lower-left area of the schematic has an underlying schematic that consists of seven IFD (input flip-flip D-type) Xilinx primitives. Using similar flip-flops, such as FDs, wastes the flip-flops in the IOBs and occupies valuable CLB resources.

Figure 9.31 SWITCH7 Schematic Using Input Flip-Flops

Saving the Calc Schematic

Before continuing, save the changes made to Calc by doing a “write,” as shown earlier in this tutorial.