The OSC (X3000A/L), OSC4 (XC4000E/L/EX/XL/XV/XLA, Spartan, and SpartanXL) and OSC5 (XC5200) oscillator components do not have Verilog simulation models associated with them. For OSC, the clock signal frequency is derived from an external crystal-controlled oscillator. The OSC4 and OSC5 are internal oscillators, and are useful in applications in which timing is not critical.
To simulate these oscillators, you must reference the net attached to the output of the oscillator component. For example, for an oscillator output net named osclk attached to an oscillator symbol (OSC, OSC4, or OSC5) with a timescale unit of 1ns, use the Always block to emulate an oscillator with a 10 Mhz clock frequency. Toggle this net at the desired frequency in your Verilog test fixture using the Force command, as shown in the following example.
force osclk = 1`b0;
always #100 force osclk = ~osclk;
