This appendix contains definitions and explanations for terms commonly used in the Hardware Debugger program.
A debugging mode in which you capture data without controlling your system clock through the Hardware Debugger.
A synonym for a configuration bitstream file.
A data stream, also called BIT file, that contains location information of logic on a device, that is, the placement of CLBs, IOBs, TBUFs, pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream programs the device.
A bitstream file has a .bit extension.
The pin of the configuration cable that connects the configuration clock to the device.
XChecker clock input pin. This pin connects the system clock to the XChecker cable. The frequency of this clock must be in the range of 120 kHz to 10 MHz. Connecting the system clock to the CLKI pin allows the Hardware Debugger to control the system clock so that snapshots are captured while the design is in a known state. If the clock source is external, the clock signal is connected to the CLKI pin; if it is internal, the clock signal is generated by the XChecker cable electronics.
XChecker clock output pin. This pin connects to the destination of the target system clock. Connecting the CLKO pin to the system clock allows the Hardware Debugger to control the system clock so that snapshots are captured while the design is in a known state.
A record of the commands that you executed during a Hardware Debugger session.
A dialog box in the Hardware Debugger that consists of buttons and fields for debugging purposes. The control panel is displayed if the Hardware Debugger detects that readback is enabled for a design. The control panel commands offer an alternative to the Debug menu commands.
The process of reading back or probing the states of a configured device to ensure that the device is behaving normally while in circuit.
The Data In pin of the configuration cable connects to the DIN pin of your target device. In serial mode, the DIN pin loads the bitstream data to the target FPGA.
This pin connects to the DONE pin of your target FPGA. It indicates the completion of the configuration process. During configuration, this pin is Low. After configuration, this pin is High.
Configuring or programming a device by sending bitstream data to the device.
The dual function Done/Program pin of your configuration cable. The pin connects to the D/P pin on your target device. As an input, D/P=0 is used to initiate a device reconfiguration. As an output, D/P=1 signals the end of configuration.
The clock connected to the XChecker CLKI pin that the Hardware Debugger uses for synchronous mode debugging. To use an external clock, connect the system clock to the XChecker cable using the CLKI pin and connect the XChecker CLKO pin to the system clock loads.
Ground (0 volt) pin of the configuration cable. This pin connects to the Ground pin of a power supply.
A combination of signals that have a common output. In the case of a counter, for example, the different signals that produce the actual counter values can be grouped under the same name and share a common representation.
Initialization pin on your configuration cable. This pin is connected to the INIT pin of your target device indicating when a device is ready to receive configuration data after power up. During configuration, INIT=0 indicates a configuration error.
The clock provided by the XChecker cable. This clock is generated in the XChecker cable electronics and is output on the CLKO pin. It is available in synchronous mode and is controlled from the Hardware Debugger.
The logic allocation file, which indicates the bitstream position of elements that can be probed, such as latches, flip-flops, and IOB inputs and outputs. The Hardware Debugger uses this file to locate signal values inside a readback bitstream. This file is created during the implementation process if readback is enabled.
The background against which other windows are displayed in the Hardware Debugger.
The area located at the top of the Hardware Debugger window. It includes the File, Cable, Download, Debug, View, Window, and Help menus. Refer to the “Menu Commands” chapter for information on the menu commands.
The number of clocks that occur between snapshots. When capturing multiple snapshots during synchronous mode debugging, the number of snapshots is used as a trigger for capturing each snapshot.
The process of examining the signal states of an FPGA device.
The Program pin of your configuration cable provides a reprogram pulse to XC4000 and XC5200 devices when connected to the PROG pin of the device.
A PROM file is the file output by the PROM File Formatter, which can be used to program one or more devices. The PROM File Formatter supports the following PROM file formats: MCS (Intel MCS-86), EXO (Motorola EXORMacs), TEKHEX (Tektronix hexadecimal), and HEX.
A raw BIT format file, the ASCII version of the BIT file.
The process of reading the logic downloaded to an FPGA device. There are two types of readbacks.
The readback data pin of the XChecker cable. This pin connects to the RDATA pin of the device. When connected, the pin reads data from the programmed target device.
The Reset pin of the XChecker cable connects to the RST pin of the target device. This pin is driven Low by the Hardware Debugger after configuration to initialize the target XC3000 FPGA internal latches and flip-flops. After configuration, this pin can be used as an active-Low reset when debugging XC4000 and XC5200 devices.
For XC4000 and XC5200 devices, the FPGA expects an active-High reset, but the Hardware Debugger produces an active-Low reset pulse. Users should invert the reset pulse before driving the GSR pin on the STARTUP symbol.
The readback trigger pin of the XChecker cable. This pin connects to the device RTRIG pin. When the XChecker cable drives this pin High, the pin initiates a readback on the target FPGA.
Readback data that contains the values of all storage elements, CLB outputs, and IOB inputs and outputs of a design at a point in time.
In the waveform window, each snapshot is marked by a red triangle.
The values stored in the memory elements of a device (flip-flops, latches, RAMs, CLB outputs, and IOBs) that represent the state of that device for a particular readback. To each state there corresponds a specific set of logical values.
The field located at the bottom of the Hardware Debugger window. It provides information about the commands that you are about to select or that are already being processed.
A debugging mode in which you use the XChecker cable to control your system clock so that snapshots can be captured while the design is in a known state.
In the Hardware Debugger, an XChecker cable pin reserved for future use. It can be used as a digital probe point using the Cable 
Logic Level of Pins command.
In the Hardware Debugger, an XChecker cable pin reserved for future use. It can be used as a digital probe point using the Cable Logic Level of Pins command.
In the Hardware Debugger, an XChecker cable pin reserved for future use. It can be used as a digital probe point using the Cable Logic Level of Pins command.
A field located under the menu bar at the top of the main window. It contains a series of buttons that execute some of the most frequently used commands. These buttons constitute an alternative to the menu commands.
The external trigger pin of the XChecker cable. This pin is connected to an external signal used as a trigger. A Low to High transition on this pin signals the XChecker cable to initiate a readback.
A signal that tells the Hardware Debugger to read a snapshot.
Power (5 volt) pin of the XChecker cable. This pin connects to the power pin of a 5 volt power supply.
The process of reading back the configuration data and comparing it to the original downloaded design to ensure that all of the design was received by the device.
The graphical representation of one or more readbacks. Usually, you select a set of signals and a set of readbacks for display. Each readback represents a particular state of the memory elements of the device.
