Design and Hardware Considerations

Before using the Hardware Debugger, you must be aware of the requirements summarized in the following table for the design entry phase. These requirements are dealt with in detail in the “Design Preparation” chapter and the “Connecting Your Cable” chapter.

Table 1_2 Requirements for Hardware Debugger Operations

	Downloading	Verification	Debugging
File Types	BIT, RBT, PROM	BIT, LL
Design symbols for XC4000/XC5200 devices	No symbols required	READBACK STARTUP ¹ 1. Optional. Use the STARTUP symbol to connect the design's global reset to the GSR (XC4000) or GR (XC5200) pin on the XChecker RESET. An inverter must be inserted in front of the GSR or GR pin to interface the active-Low XChecker reset with the active-High GSR/GR reset.
Configuration options for XC3000 devices	Enable pull-up resistor on DONE/PROG pin	- Enable pull-up resistor on DONE/ PROG pin - Set Readback Mode to Once or On Command or use the -l option in BitGen
Configuration options for XC4000/XC5200 devices	Enable pull-up on DONE pin	- Set readback clock to CClk - Enable the Enable Bitstream Verification and In-Circuit Hardware Debugging option or use the -l option in BitGen
Cable Type	XChecker, serial, or parallel cables	XChecker cable
Pins Used	VCC GND CCLK D/P (DONE) DIN PROG (XC4000/XC5200) INIT RST	VCC GND CCLK RT RD	VCC GND CCLK RT RD TRIG² 2. Optional CLKI³ 3. Optional CLKO⁴ 4. Optional
Configuration Mode	Slave	N/A	N/A

Design Entry and Bitstream Generation

You will need access to certain signals depending on whether you generate a design for downloading only or for downloading and debugging.

For downloading only, use any of the three configuration data file types (BIT, RBT, or PROM) and any download cable. You do not need any special symbols or configuration options to generate the configuration data.

NOTE
To create a PROM file using multiple bitstreams, use the PROM File Formatter. For more information on how to use the PROM File Formatter, see the PROM File Formatter Reference/User Guide.
For single device verification or debugging, use a BIT file, enable readback to generate an LL file in your design directory, and for XC4000/XC5200 devices, include the READBACK symbol in your design and optionally, the STARTUP symbol. In addition, you must use an XChecker cable.

Hardware Considerations

Before using the Hardware Debugger, you need to decide what hardware to use.

Configuration Mode

When using the download cables to configure a device or daisy chain of devices, you must set the configuration mode of the devices being configured to slave serial. You must set M0, M1, and M2 to VCC. If you intend to use them as user I/Os, use 4.7 kilohm pull-ups. Refer to the Development System User Guide or The Programmable Logic Data Book for information on how to set the mode pins.

Target Board Selection

Your target board can be either a Xilinx FPGA demonstration board or your own board. The demonstration boards can be used to test most designs.

If you are using an FPGA demonstration board, set up the board as explained in the “CALC Tutorial” chapter.

You must set the board switches and connect the appropriate cable.
If you are using your own board, you must configure the board and connect the appropriate cable. Refer to the “Connecting Your Cable” chapter for information.

Single or Multiple Device Configuration

You can configure one device or a daisy chain. See the “XChecker Operation Mode Connections” table in the “Connecting Your Cable” chapter for information on pin connections.

To configure a single device, connect the pins as specified for that particular device type.
For a daisy chain of devices, connect the pins of the lead device for downloading. Connect the pins of the slave devices to the lead device as described in the The Programmable Logic Data Book.

Cable Connections

You can perform three main operations using the Hardware Debugger. Each operation requires a specific setup and, in the case of verification and debugging, a particular download cable. Refer to the “XChecker Operation Mode Connections” table in the “Connecting Your Cable” chapter for cable connections information for each operation.

Downloading

Connect the cable header to the pin assembly on your target board that is connected to the FPGA configuration pins. If you have an XChecker cable, connect a cable header connector to the outermost slot of the XChecker cable assembly.

Verification

For this operation, you must use an XChecker cable. Connect both header connectors to the pin assembly on your target board.

Debugging

For this operation, you must use an XChecker cable. Connect both header connectors to the pin assembly on your target board. You need to connect the CLKI and CLKO pins only if you are debugging in synchronous mode. You can disconnect them for asynchronous mode debugging.

NOTE

The RST pin is only required for XC3000 downloading and debugging. You do not need to connect it for XC4000 or XC5200 downloading. Optionally, you can use it as a system design reset for XC4000 or XC5200 debugging.