Foundation Design Tutorial

The Xilinx Foundation Software Series contains the CPLD Jcounter tutorial, which includes the following five design entry methods.

• JCT_SCH (schematic only)
  
  
• JCT_ABL (ABEL only)
  
  
• JCT_SABL (schematic with ABEL macro)
  
  
• JCT_VHD (VHDL only)
  
  
• JCT_SVHD (schematic with VHDL macro)
  
  

Example I: Schematic Design Entry

Example 1 shows the readme.txt file that is located in the project directories of the Jcounter tutorial designs in the Xilinx Foundation Series^™ software. Use these tutorial designs to learn the ISP design flow.

Schematic With VHDL Macro Design

   JCT_SVHD is a simple 8-bit Johnson counter

   DESIGN FLOW: Schematic (JCT_SVH1.SCH) with XVHDL macro (JCOUNTER.VHD)

   TARGET DEVICE: XC9536-VQ44 (any speed)

   I/O Pins: 
     CLK   : input free-running clock
     Q0-Q7 : counter outputs

   OPERATION: 
     The counter is triggered on rising edge of the clock
     (CLK).
     The following is the sequence of states on outputs Q
     Q7-Q0:
       00000000
       00000001
       00000011
       00000111
       00001111
       00011111
       00111111
       01111111
       11111111
       11111110
       11111100
       11111000
       11110000
       11100000
       11000000
       10000000
       00000000  (repeats)

   SIMULATION WAVEFORMS:
     JCT_FUNC : functional simulation of design before 
     implementation.
     JCT_TIME : timing simulation results after 
     implementation.

   TUTORIAL:
     This project is used as one of the example designs
     described in the CPLD Design Flow tutorial in the
     Foundation Series On-Line Help System.

   DEMO BOARD:
     The JEDEC programming file produced by this project
     can be downloaded into the CPLD Demo Board 
     (HW-CPLD-DEMOBD).

Example 2: VHDL Design Entry

Example 2 shows the same design, done in VHDL while using Xilinx Foundation software.

   library IEEE;
   
   use IEEE.std_logic_1164.all 
   
   library metamor; 
   
   use metamor.attributes.all;    
   
   entity jcounter is
     
      port  ( 
   
          clk:in STD_LOGIC;
     
          Dout: buffer STD_LOGIC_VECTOR (7 downto 0)    
  
     );    
     
   -- Can use attributes to assign pin locations in    --- Foundation VHDL 
   attribute pinnum of Dout:signal is     "p13,14,16,18,19,20,21,22";     
 
   end jcounter;    
     
   architecture jcounter_arch of jcounter is    
 
   begin 
   
      if CLK' event and CLK='1' then--CLK rising edge
    
         Dout (7 downto 1) <= Dout (6 downto 0);--shift --- register 
   
         Dout (0) <= not Dout (7);--Last bit inverted ---- back into first bit     
      end if;
    
   end process;
    
   end jcounter_arch;