FTRSE

Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set

FTRSE is a toggle flip-flop with toggle and clock enable and synchronous reset and set. When the synchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is reset Low. When the synchronous set input (S) is High and R is Low, clock enable input (CE) is overridden and output Q is set High. (Reset has precedence over Set.) When toggle enable input (T) and CE are High and R and S are Low, output Q toggles, or changes state, during the Low-to-High clock transition.

The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs					Outputs
R	S	CE	T	C	Q
1	X	X	X		0
0	1	X	X		1
0	0	0	X	X	No Chg
0	0	1	0	X	No Chg
0	0	1	1		Toggle

Figure 5.65 FTRSE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

Figure 5.66 FTRSE Implementation XC9000