This section discusses techniques for specifying device I/O pins using both general-purpose and special-purpose input/output buffer symbols.
To represent an ordinary device input, use an IPAD connected to one IBUF symbol. The IBUF can then connect to any number of on-chip logic symbols. An I/O pin of the CPLD device will be allocated to receive the input, and its output driver will be permanently disabled.
To represent an ordinary device output, use an OBUF that is driven by exactly one on-chip logic source. Connect the output of the OBUF to an OPAD symbol. To specify a tristate device output, use an OBUFE or OBUFT instead of the OBUF, and connect its enable/disable input to any on-chip logic source. An I/O pin will be allocated to drive the signal, either always active (if OBUF) or controlled by your enable/disable signal, and the input received by the device pin will be ignored.
To represent a bidirectional device I/O, use an OBUFE or OBUFT whose output is connected to both an IOPAD symbol and to the input of an IBUF, as shown in the “Bidirectional I/O Pin” figure.
Figure 2.1 Bidirectional I/O Pin |  |
It is important that you label the nets that represent device input/output pins in your design. These are the nets connecting between IPAD and IBUF symbols, and between OBUF and OPAD symbols. These names will appear in the fitter reports as your pin names and will be used as signal names during simulation.
Do not use the reserved names “GND,” “VCC,” "PRLD" or "MRESET" as labels for any nets or component instances in your design.
To use a device input as a clock source, you can simply connect an IBUF to the clock input of one or more flip-flops in your design. The fitter automatically uses one of the global clock pins (GCK) of the CPLD whenever possible.
A clock input signal may pass through an inverter to perform negative-edge clocking and the fitter can still use a global clock pin to implement it. The same global clock input may even be used both inverted and non-inverted to clock different flip-flops on opposite edges of the clock signal, as shown in “Input CLK1 can be Optimized onto a Global Clock Pin (GCK)” figure. Global clock inputs may also be used as ordinary input signals to other logic elsewhere in the design.
Figure 2.2 Input CLK1 can be Optimized onto a Global Clock Pin (GCK) | |
If a device input passes through any logic function (other than an inverter) before it is used as a clock by any flip-flop, the input cannot be routed using the global clock path. Instead, the clock signal will be routed through the logic array for all flip-flops clocked by such a device input.
There are a limited number of global clock pins on each CPLD device (consult the device data sheet). If you need to explicitly control the use of global clock pins, you can use the BUFG symbol in place of an IBUF. You could alternatively apply the BUFG=CLK attribute to an IBUF symbol or the pad net.
The global clock pins provide much shorter clock-to-output delays than clocks routed through the logic array. Routing a clock through the logic array also uses up one extra p-term for each flip-flop.
You can prevent the fitter from automatically mapping IBUF symbols to the global clock pins. On the Design Manager graphical interface, go to the Flow Engine and select:
Setup 
Options
The Design Implementation Option menu appears. Select:
Edit Template
Then select:
Basic Options
Lastly, place a check on the Off box adjacent to Use Global Clocks.
If global clock optimization is disabled, IBUF inputs used as clocks will always pass through the logic array. You can still use BUFG symbols or the BUFG=CLK attribute to explicitly specify global clock inputs.
To use a device input to control tristate device outputs, you can simply connect an IBUF to the enable/disable input of one or more OBUFE or OBUFT symbols in your design. The fitter automatically uses one of the global tristate control pins (GTS) of the CPLD whenever possible.
A global tristate control input signal may pass through an inverter or control the disable input (T) of an OBUFT symbol to perform an active-low output-enable. The same tristate control input may even be used both inverted and non-inverted to enable alternate groups of device outputs, as shown in the “Input OE2 can be Optimized onto a Global Tristate Control Pin (GTS)” figure. Global tristate control inputs may also be used as ordinary input signals to other logic elsewhere in the design.
Figure 2.3 Input OE2 can be Optimized onto a Global Tristate Control Pin (GTS) | |
If a device input passes through any logic function (other than an inverter) before it is used as a tristate control by any output, the input cannot be routed using the global tristate control path. Instead, the output enable signal will be routed through the logic array, for all device outputs controlled by such an input.
There are a limited number of global tristate control pins on each XC9500 device (consult the device data sheet). If you need to explicitly control the use of global tristate control pins, you can use the BUFGTS symbol. You can alternatively apply the attribute BUFG=OE to an IBUF symbol or the pad net.
The global tristate control pins provide much shorter input-to-output-enable delays than tristate controls routed through the logic array. Routing a tristate control signal through the logic array also uses up one extra p-term for each output.
You can prevent the fitter from automatically using the global tristate control pins. In the Design Manager, go to the Flow Engine and select:
Setup Options
The Design Implementation Option menu appears. Select:
Edit Template
Then select:
Basic Options
Lastly, disable the box adjacent to Use Global Output Enables.
If global output enable optimization is disabled, IBUF inputs used for tristate control will always pass through the logic array. You can still use BUFGTS symbols or the BUFG=OE attribute to explicitly specify global tristate control inputs.
To use a device input as an asynchronous clear or preset source, you can simply connect an IBUF to the CLR or PRE input of one or more flip-flops in your design. The fitter automatically uses the global set/reset pin (GSR) of the CPLD whenever possible. A global set/reset input signal may pass through an inverter to perform active-low clear or preset. A global set/reset inputs may also be used as an ordinary input signal to other logic elsewhere in the design.
If a device input passes through any logic function other than an inverter before it is used as an asynchronous clear or preset by any flip-flop, the input cannot be routed using the global set/reset path. Instead, the clear or preset signal will be routed through the logic array for all flip-flops controlled by such an input. Routing a clear or preset through the logic array uses up one extra p-term for each flip-flop.
There is only one global set/reset pin on each XC9500 device. If you need to explicitly control the use of the global set/reset pin, you can use the BUFGSR symbol in place of an IBUF. You can alternatively apply the attribute BUFG=SR to an IBUF symbol or the pad net.
You can prevent the fitter from using the global set/reset pin. In the Design Manager, disable the Use Global Set/Reset option in the Basic Options template of the Flow Engine.
If a flip-flop has both a clear and preset input and you assert both the clear and preset concurrently, its Q-output is unpredictable. This is because the fitter may arbitrarily invert the logic stored in a flip-flop to achieve better logic optimization. Individual clear and preset operations still produce the correct final logic state as dictated by the user design. Functional simulation does not accurately predict the ultimate behavior of the chip when clear and preset are asserted concurrently. Timing simulation, however, is performed after logic optimization and behaves exactly as the chip will when programmed.
When targeting an XC9500 device, any FDCE or FDPE primitives in your design will be expanded into an ordinary D-type flip-flop with its Q-feedback multiplexed into its D-input. This implementation will be similar to the way the FDCPE macro is expanded in the XC9000 schematic library.
When targeting an XC9500XL device, logic connected to the clock enable (CE) input of FDCE and FDPE primitives in your design will be unconditionally implemented using the clock enable p-term of the XC9500XL macrocell. Only the FDCE and FDPE primitives use the clock enable p-term.
If you use FDCE or FDPE components and target an XC9500XL device, you may find that the logic connected to the clock enable input on some components may not get optimized into the same macrocell as the flip-flop. The XC9500XL macrocell contains only a single product-term to implement clock enable input logic. The CPLD fitter does not attempt transform your clock enable input logic onto the D-input of the flip-flop if it cannot be completely implemented using the clock enable p-term. In general, only primary inputs (device input pins or macrocell feedbacks), their complements or positive-logic AND-gate functions of primary inputs or their complements can be completely implemented using the p-term. If you connect a more complex logic function to the clock enable input of an FDCE or FDPE component and it does not get completely implemented on the clock enable p-term, your design may incur extra macrocell resources and combinational macrocell feedback delays.
If you have an existing CPLD schematic containing FDCE or FDPE components and you do not want the logic connected to the CE input of the components to be implemented using the clock enable p-term in the XC9500XL macrocell, you can simply replace FDCE or FDPE components in your schematic with FDCPE components from the XC9000 library. The FDCPE component is a macro which always gets expanded into a simple D-type flip-flop with its Q-feedback multiplexed into its D-input; the clock enable p-term is not used. After substitution, the unconnected PRE or CLR input to the FDCPE will be automatically trimmed away by the CPLD fitter.
XC9500 CPLD devices can emulate tristate bussing between on-chip signal sources by gating the macrocell feedback to the FastCONNECT structure. (Macrocell feedback signals are never physically in a high-impedance state.) Multiple feedbacks emulating tristate signals can be wire-ANDed in the FastCONNECT to emulate bussing and tristate multiplexing. When an on-chip tristate signal is "disabled", the macrocell feedback is forced High so that it does not affect the wire-AND. The signal on the wire-AND will therefore follow the logic value of the "enabled" feedback.
To represent tristate multiplexing (bussing) in the schematic, tie together the outputs of multiple tristate buffer symbols, like BUFE and BUFT, as in the “Correct On-Chip Tristate Multiplexing” figure. You cannot, however, connect such tied signals directly to an output buffer; instead you must pass a tied signal through a logic symbol, like BUF, before driving an output port.
XC9500XL does not support internal tristate bussing. Never use BUFE or BUFT components in an XC9500XL design. On-chip tristate bussing is supported by some of the FPGA device families.
Figure 2.4 Correct On-Chip Tristate Multiplexing | |
If your design calls for tristate bussing of multiple signals driven off-chip, it may be better to output each signal source on its own tristate output pin and tie the pins together off-chip, as shown in the “Correct Off-Chip Tristate Multiplexing of CPLD Outputs” figure. You cannot connect more than one signal source to the same OBUF or OPAD, as shown in the “Incorrect Tristate Multiplexing of CPLD Outputs” figure.
XC9500XL does not support internal tristate bussing. Never use BUFE or BUFT components in an XC9500XL design. On-chip tristate bussing is supported by some of the FPGA device families.
Figure 2.5 Correct Off-Chip Tristate Multiplexing of CPLD Outputs | |
Figure 2.6 Incorrect Tristate Multiplexing of CPLD Outputs | |
