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Behavioral Modules

Behavioral modules are user-generated symbols functionally defined by some logic description other than a schematic, typically Boolean equations or HDL. Some reasons why you may want to use behavioral modules in your schematic are:

The Xilinx CPLD fitter also accepts entirely behavioral designs which use no schematics. Similar to behavioral modules for schematic designs, behavioral designs are expressed using Boolean equations or HDL and compiled using a PLD compiler (like XABEL) or a logic synthesis tool. Unlike behavioral modules, behavioral designs contain all the device I/O port information in its behavioral description.

This manual describes only schematic-based designs and the behavioral modules which may be contained in them. The procedures for creating behavioral modules in CPLD schematics is essentially the same as for all other Xilinx device families.

Compiling Behavioral Logic

The equation or HDL files defining behavioral modules must be compiled before they can be used by the fitter. There are a variety of PLD compilers and synthesis tools that support design entry for CPLD devices.

Behavioral compilers which are compatible with the CPLD fitter translate their logic descriptions into EDIF or XNF formatted netlists.

NOTE

Previous versions of the CPLD fitter used the Plusasm equation language as an interchange language in place of XNF or EDIF for some behavioral compilers, such as XABEL. Plusasm is still recognized and processed by this version of the fitter for the sake of existing behavioral modules based on that interface. However, future versions of the software will not support Plusasm and it should not be used when creating any new behavioral modules.

If the behavioral compiler tool supports the development of completely behavioral designs, make sure you select the appropriate mode of operation or compilation flow for producing logic modules, not stand-alone designs. The netlist produced by the compiler must not contain device I/O pin information. If any of the terminal nodes (inputs or outputs) of your behavioral module are to be connected to CPLD device pins, you must use IBUF and OBUF symbols in your schematic.

NOTE

If you are using a synthesis tool to prepare a behavioral module, make sure you target the appropriate CPLD technology library.

Your compiled behavioral module file is normally stored in your project directory. You can also copy it to a user library directory if you want to use it for more than one project.

Behavioral Module Symbols in Schematics

Using a behavioral module in a schematic design involves creating a symbol to represent your logic, placing the symbol into your schematic and applying necessary attributes to identify the logic-defining file.

  1. Use the symbol editing facility of your schematic entry tool to create a symbol representing your behavioral logic. Generally, the name of your symbol will be the name of the behavioral module, although this is not mandatory.

    Place a pin on your symbol for each terminal node (input or output port) in your behavioral design that needs to be connected to other logic or I/O ports in your schematic. "Buried" nodes that connect only between logic functions within the behavioral module do not require pins on your symbol.

    Some tools have commands or utilities that automatically generate symbols based on the terminal nodes defined in your behavioral module.

  2. Some schematic entry tools distinguish between two types of symbols: primitive symbols (sometimes called "module") and hierarchical symbols (sometimes called "composite") that link to schematics beneath them. When creating a symbol to represent a behavioral module, create it as a primitive symbol.

    When your symbol is complete, store it in your project directory or in a user library directory if you want to use the symbol in more than one project.

  3. Instantiate the new symbol one or more times in your design schematic and connected it to other logic and I/O buffers as needed. As with library symbols, unused input pins on your behavioral module symbol should be tied to VCC or GND.

  4. Add an attribute to each instance of a behavioral module symbol in your schematic to identify the compiled behavioral logic file. The format of the attribute is

    FILE=filename

    where filename is the name of the file produced by the behavioral compiler, either with or without extension. If the compiled file is stored in a different directory (such as a user library), include the complete directory path qualification in the FILE attribute.

Behavioral Module Example for Viewlogic

This simple example shows you how to develop a behavioral module defined by an ABEL-language equation file and represented by a custom symbol in a Viewlogic schematic.

  1. Create the following ABEL file named regxor.abl. 

         MODULE regxor 
      TITLE `Registered XOR gate' 
      IO pin; 
      I1 pin; 
      CLK pin; 
      Q pin istype `reg'; 
      EQUATIONS 
      Q := IO $ I1; 
      Q.C = CLK; 
      end

  2. Compile the file to create an EDIF netlist file named regxor.edn.

  3. In Viewdraw, open a symbol window and create a new symbol named regxor as shown in the “The REGXOR Symbol” figure. The symbol has three input pins and one output pin corresponding to the pins defined in the ABEL equation file.

    Figure 2.7 The REGXOR Symbol

  4. Make sure the symbol is defined as a primitive. For example, if you are using WorkView Office, use the Change Symbol Type Module command to indicate that there is no underlying schematic for the symbol. Then save the symbol in your project directory.

  5. Instantiate the symbol in your schematic and connect its input and output pins to logic and/or I/O buffers in your design.

  6. Select the regxor component in your schematic and add the attribute FILE=regxor.

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