Verilog uses keywords to interpret an input file. You cannot use these words as user variable names unless you use an escaped identifier. For more information, see the “Identifiers” section of this chapter.
| always | and | assign | begin |
| buf | bufif0 | bufif1 | case |
| casex | casez | cmos | deassign |
| default | defparam | disable | else |
| end | endcase | endfunction | endmodule |
| endprimitive | endtable | endtask | event |
| for | force | forever | fork |
| function | highz0 | highz1 | if |
| initial | inout | input | integer |
| join | large | medium | module |
| nand | negedge | nmos | nor |
| not | notif0 | notif1 | or |
| output | parameter | pmos | posedge |
| primitive | pulldown | pullup | pull0 |
| pull1 | rcmos | reg | release |
| repeat | rnmos | rpmos | rtran |
| rtranif0 | rtranif1 | scalared | small |
| strong0 | strong1 | supply0 | supply1 |
| supply1 | table | task | time |
| tran | tranif0 | tranif1 | tri |
| triand | trior | trireg | tri0 |
| tri1 | vectored | wait | wand |
| weak0 | weak1 | while | wire |
| wor | xnor | xor |
