Chapter 6

Sequential Statements

Sequential statements are interpreted one after another, in the order in which they are written. VHDL sequential statements can appear only in a process or subprogram. A VHDL process is a group of sequential statements; a subprogram is a procedure or function.

This chapter describes and illustrates the various types of sequential statements. The chapter is divided into the following sections.

• “Processes”
  
  
• “Assignment Statements”
  
  
• “Variable Assignment Statements”
  
  
• “Signal Assignment Statements”
  
  
• “If Statements”
  
  
• “Case Statements”
  
  
• “Loop Statements”
  
  
• “Next Statements”
  
  
• “Exit Statements”
  
  
• “Subprograms”
  
  
• “Return Statements”
  
  
• “Mapping Subprograms to Components (Entities)”
  
  
• “Wait Statements”
  
  
• “Null Statements”