Overview

The Design Manager is the top level software module in the Xilinx Alliance Series Development System. Use the Xilinx Development System tool suite to implement a design into a Xilinx device. The Design Manager provides access to all the tools you need to read a design file from a design entry tool and implement it in a Xilinx device. The Design Manager performs the following functions.

• Organizes and manages your design implementation data
  
  
• Creates multiple design versions for management of design changes
  
  
• Creates multiple implementation revisions for management of implementation strategies
  
  
• Provides access to reports
  
  
• Manages data for and provides access to the following tools. The tools differ for FPGA and CPLD families.
  
  
  • Flow Engine (FPGA and CPLD)
    
    
  • Timing Analyzer (FPGA and CPLD)
    
    
  • Floorplanner (All XC4000 families, Virtex, Spartan/XL, and Spartan2 FPGA families only)
    
    
  • PROM File Formatter (FPGA)
    
    
  • Hardware Debugger (FPGA)
    
    
  • FPGA Editor (FPGA)
    
    
  • Chip Viewer (CPLD)
    
    
  • JTAG Programmer (All XC4000 families, XC5200, Virtex, Spartan/XL, and Spartan2 FPGA families and CPLD families)
    
    

The Design Manager manages your Xilinx designs. The Flow Engine implements your designs. The Flow Engine is closely integrated with the Design Manager, sharing many of the same menus and dialog boxes. You can use the Design Manager and Flow Engine together to perform the following functions.

• Target different devices
  
  
• Generate and export timing simulation data for external simulation tools
  
  
• Generate and export configuration data